DSPIC30F6011A-30I/PT Microchip Technology Inc., DSPIC30F6011A-30I/PT Datasheet - Page 141
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DSPIC30F6011A-30I/PT
Manufacturer Part Number
DSPIC30F6011A-30I/PT
Description
DSP, 16-Bit, 132 KB Flash, 6KB RAM, 52 I/O, TQFP-64
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F6012A-30IPT.pdf
(238 pages)
Specifications of DSPIC30F6011A-30I/PT
A/d Inputs
16-Channels, 12-Bit
Cpu Speed
30 MIPS
Eeprom Memory
2K Bytes
Input Output
52
Interface
CAN, I2C, SPI, UART/USART
Ios
52
Memory Type
Flash
Number Of Bits
16
Package Type
64-pin TQFP
Programmable Memory
132K Bytes
Ram Size
6K Bytes
Timers
5-16-bit, 2-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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19.9
The module has 2 internal Power modes.
When the ADON bit is ‘1’, the module is in Active mode;
it is fully powered and functional.
When ADON is ‘0’, the module is in Off mode. The dig-
ital and analog portions of the circuit are disabled for
maximum current savings.
In order to return to the Active mode from Off mode, the
user must wait for the ADC circuitry to stabilize.
19.10 ADC Operation During CPU Sleep
19.10.1
When the device enters Sleep mode, all clock sources
to the module are shutdown and stay at logic ‘0’.
If Sleep occurs in the middle of a conversion, the con-
version is aborted. The converter will not continue with
a partially completed conversion on exit from Sleep
mode.
Register contents are not affected by the device
entering or leaving Sleep mode.
The ADC module can operate during Sleep mode if the
ADC clock source is set to RC (ADRC = 1). When the
RC clock source is selected, the ADC module waits one
instruction cycle before starting the conversion. This
allows the SLEEP instruction to be executed which elim-
inates all digital switching noise from the conversion.
When the conversion is complete, the CONV bit will be
cleared and the result loaded into the ADCBUF register.
FIGURE 19-5:
© 2006 Microchip Technology Inc.
RAM Contents:
Read to Bus:
Module Power-down Modes
and Idle Modes
Signed Fractional
ADC OPERATION DURING CPU
SLEEP MODE
Signed Integer
Fractional
Integer
ADC OUTPUT DATA FORMATS
dsPIC30F6011A/6012A/6013A/6014A
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d11 d11 d11 d11 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
0
0
0
0
Preliminary
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
If the ADC interrupt is enabled, the device will wake-up
from Sleep. If the ADC interrupt is not enabled, the
ADC module will then be turned off, although the
ADON bit will remain set.
19.10.2
The ADSIDL bit selects if the module will stop on Idle
or continue on Idle. If ADSIDL = 0, the module will con-
tinue operation on assertion of Idle mode. If ADSIDL =
1, the module will stop on Idle.
19.11 Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the ADC module to be turned off, and any
conversion and sampling sequence is aborted. The val-
ues that are in the ADCBUF registers are not modified.
The ADC Result register will contain unknown data
after a Power-on Reset.
19.12 Output Formats
The ADC result is 12 bits wide. The data buffer RAM is
also 12 bits wide. The 12-bit data can be read in one of
four different formats. The FORM<1:0> bits select the
format. Each of the output formats translates to a 16-bit
result on the data bus.
ADC OPERATION DURING CPU
IDLE MODE
0
0
DS70143C-page 139
0
0
0
0
0
0
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