LTC485CS8 Linear Technology, LTC485CS8 Datasheet - Page 8

• Manufacturer Part Number: LTC485CS8
• Description: IC TXRX INTRFC RS485 LOPWR 8SOIC
• Manufacturer: Linear Technology
• Type: Transceiverr

Specifications of LTC485CS8

• Number Of Drivers/receivers: 1/1
• Protocol: RS485
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS INFORMATION
LTC485
Basic Theory of Operation
Previous RS485 transceivers have been designed using
bipolar technology because the common mode range
of the device must extend beyond the supplies and the
device must be immune to ESD damage and latchup.
Unfortunately, the bipolar devices draw a large amount of
supply current, which is unacceptable for the numerous
applications that require low power consumption. The
LTC485 is the fi rst CMOS RS485/RS422 transceiver which
features ultralow power consumption without sacrifi cing
ESD and latchup immunity.
The LTC485 uses a proprietary driver output stage, which
allows a common-mode range that extends beyond the
power supplies while virtually eliminating latchup and
providing excellent ESD protection. Figure 9 shows the
LTC485 output stage while Figure 10 shows a conventional
CMOS output stage.
When the conventional CMOS output stage of Figure 10
enters a high impedance state, both the P-channel (P1)
and the N-channel (N1) are turned off. If the output is then
driven above V
8
CC
Figure 9. LTC485 Output Stage
LOGIC
or below ground, the P + /N-well diode
485 F09
N1
P1
V
CC
SD4
SD3
OUTPUT
D1
D2
(D1) or the N + /P-substrate diode (D2) respectively will
turn on and clamp the output to the supply. Thus, the output
stage is no longer in a high impedance state and is not
able to meet the RS485 common mode range requirement.
In addition, the large amount of current fl owing through
either diode will induce the well known CMOS latchup
condition, which could destroy the device.
The LTC485 output stage of Figure 9 eliminates these
problems by adding two Schottky diodes, SD3 and SD4.
The Schottky diodes are fabricated by a proprietary modi-
fi cation to the standard N-well CMOS process. When the
output stage is operating normally, the Schottky diodes
are forward biased and have a small voltage drop across
them. When the output is in the high impedance state and
is driven above V
D1 or D2 still turn on, but SD3 or SD4 will reverse bias
and prevent current from fl owing into the N-well or the
substrate. Thus, the high impedance state is maintained
even with the output voltage beyond the supplies. With
no minority carrier current fl owing into the N-well or
substrate, latchup is virtually eliminated under power-up
or power-down conditions.
Figure 10. Conventional CMOS Output Stage
CC
LOGIC
or below ground, the parasitic diodes
485 F10
N1
P1
V
CC
OUTPUT
D1
D2
485fh