PIC16C74B-20/L Microchip Technology Inc., PIC16C74B-20/L Datasheet - Page 15

• Manufacturer Part Number: PIC16C74B-20/L
• Description: 44 PIN, 7 KB OTP, 192 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16C74B-20/L

• A/d Inputs: 8-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 33
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 4 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2.5-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.0
4.1
The PIC16C63A/65B/73B/74B has a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. All devices covered by this data sheet
have 4K x 14 bits of program memory. The address
range is 0000h - 0FFFh for all devices.
Accessing a location above 0FFFh will cause a wrap-
around.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
FIGURE 4-1:
2000 Microchip Technology Inc.
CALL,RETURN
RETFIE,RETLW
MEMORY ORGANIZATION
Program Memory Organization
On-chip Program
Memory (Page 0)
On-chip Program
Memory (Page 1)
Interrupt Vector
Stack Level 1
Stack Level 8
RESET Vector
PC<12:0>
PIC16C63A/65B/73B/74B
PROGRAM MEMORY MAP
AND STACK
13
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
1FFFh
PIC16C63A/65B/73B/74B
4.2
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP1
and RP0 are the bank select bits.
RP1:RP0 (STATUS<6:5>)
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the SFRs.
Above the SFRs are GPRs, implemented as static
RAM.
All implemented banks contain SFRs. Frequently used
SFRs from one bank may be mirrored in another bank
for code reduction and quicker access.
4.2.1
The register file can be accessed either directly, or indi-
rectly, through the File Select Register (FSR)
(Section 4.5).
= 00
= 01
= 10
= 11
Note:
Bank0
Bank1
Bank2
Bank3
Data Memory Organization
Maintain the IRP and RP1 bits clear in
these devices.
GENERAL PURPOSE REGISTER
FILE
DS30605C-page 15