CY7B933-JXI Cypress Semiconductor Corp, CY7B933-JXI Datasheet - Page 6

• Manufacturer Part Number: CY7B933-JXI
• Description: IC RECEIVER HOTLINK 28-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink™r
• Type: Transmitter and Receiverr

Specifications of CY7B933-JXI

• Package / Case: 28-PLCC
• Protocol: Fibre Channel
• Voltage - Supply: 4.5V ~ 5.5V
• Mounting Type: Surface Mount
• Product: PHY
• Data Rate: 400 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current: 0.16 A
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Channels: 1
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 28
• Power Dissipation Pd: 650mW
• Ic Interface Type: Parallel, Serial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2907-5; CY7B933-JXI

Pin Descriptions
Table 1. CY7B923 HOTLink Transmitter
Document #: 38-02017 Rev. *H
D
(D
SC/D (D
SVS
(D
ENA
ENN
CKW
FOTO
OUTA
OUTB
OUTC
MODE
BISTEN
RP
V
V
GND
Name
CCN
CCQ
07
b  h
j
)
)
a
)
TTL In
TTL In
TTL In
TTL In
TTL In
TTL In
TTL In
PECL Out
Three-
Level In
TTL In
TTL Out
I/O
Parallel data input. Data is clocked into the Transmitter on the rising edge of CKW if ENA is LOW (or on
the next rising CKW with ENN LOW). If ENA and ENN are HIGH, a Null character (K28.5) is sent. When
MODE is HIGH, D
Special character/data select. A HIGH on SC/D when CKW rises causes the transmitter to encode the
pattern on D
the 8B/10B data alphabet. When MODE is HIGH, SC/D (D
as D
Send violation symbol. If SVS is HIGH when CKW rises, a Violation symbol is encoded and sent while
the data on the parallel inputs is ignored. If SVS is LOW, the state of D
sent. In normal or test mode, this pin overrides the BIST generator and forces the transmission of a
Violation code. When MODE is HIGH (placing the transmitter in unencoded mode), SVS (D
D
Enable parallel data. If ENA is LOW on the rising edge of CKW, the data is loaded, encoded, and sent. If
ENA and ENN are HIGH, the data inputs are ignored and the Transmitter will insert a Null character (K28.5)
to fill the space between user data. ENA may be held HIGH/LOW continuously or it may be pulsed with
each data byte to be sent. If ENA is being used for data control, ENN will normally be strapped HIGH, but
can be used for BIST function control.
Enable next parallel data. If ENN is LOW, the data appearing on D
loaded, encoded, and sent. If ENA and ENN are HIGH, the data appearing on D
of CKW will be ignored and the Transmitter will insert a Null character to fill the space between user data.
ENN may be held HIGH/LOW continuously or it may be pulsed with each data byte sent. If ENN is being
used for data control, ENA will normally be strapped HIGH, but can be used for BIST function control.
Clock write. CKW is both the clock frequency reference for the multiplying PLL that generates the
high-speed transmit clock, and the byte rate write signal that synchronizes the parallel data input. CKW
must be connected to a crystal controlled time base that runs within the specified frequency range of the
Transmitter and Receiver.
Fiber optic transmitter off. FOTO determines the function of two of the three PECL transmitter output pairs.
If FOTO is LOW, the data encoded by the Transmitter will appear at the outputs continuously. If FOTO is
HIGH, OUTA and OUTB are forced to their “logic zero” state (OUT+ = LOW and OUT = HIGH), causing
a fiber-optic transmit module to extinguish its light output. OUTC is unaffected by the level on FOTO, and
can be used as a loop-back signal source for board-level diagnostic testing.
Differential serial data outputs. These PECL 100 K outputs (+5 V referenced) are capable of driving
terminated transmission lines or commercial fiber optic transmitter modules. Unused pairs of outputs can
be left open, or wired to V
controlled by the level on FOTO, and will remain at their “logical zero” states when FOTO is asserted.
OUTC± is unaffected by the level on FOTO. (OUTA+ and OUTB+ are used as a differential test clock input
while in Test mode, that is, MODE = UNCONNECTED or forced to V
Encoder mode select. The level on MODE determines the encoding method to be used. When wired to
GND, MODE selects 8B/10B encoding. When wired to V
pattern on D
the internal bit-clock generator is disabled and OUTA+/OUTB+ become the differential bit clock to be used
for factory test. In typical applications MODE is wired to V
BIST enable. When BISTEN is LOW and ENA and ENN are HIGH, the transmitter sends an alternating
1–0 pattern (D10.2 or D21.5). When either ENA or ENN is set LOW and BISTEN is LOW, the transmitter
begins a repeating test sequence that allows the Transmitter and Receiver to work together to test the
function of the entire link. In normal use this input is held HIGH or wired to V
free-running pattern generator that need not be initialized, but if required, the BIST sequence can be
initialized by momentarily asserting SVS while BISTEN is LOW. BISTEN has the same timing as D
Read pulse. RP is a 60% LOW duty-cycle byte-rate pulse train suitable for the read pulse in CY7C42X
FIFOs. The frequency on RP is the same as CKW when enabled by ENA, and duty cycle is independent
of the CKW duty cycle. Pulse widths are set by logic internal to the transmitter. In BIST mode, RP will
remain HIGH for all but the last byte of a test loop. RP will pulse LOW one byte time per BIST loop.
Power for output drivers.
Power for internal circuitry.
Ground.
Description
j
input. SVS has the same timing as D
07
.
07
a–j
goes directly to the shifter. When left floating (internal resistors hold the input at V
as a control code (Special Character), while a LOW causes the data to be coded using
0, 1, ...7
become D
CC
to reduce power, if the output is not required. OUTA± and OUTB± are
b, c,...h
07
, respectively.
.
CC
CC
a
) acts as D
, data inputs bypass the encoder and the bit
or GND.
07
CC
07
a
at the next rising edge of CKW is
CY7B923, CY7B933
input. SC/D has the same timing
/2).
and SC/D determines the code
CC
07
. The BIST generator is a
at the next rising edge
j
) acts as the
Page 6 of 40
CC
0-7
/2)
.
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