PIC16C73A-04/SP Microchip Technology Inc., PIC16C73A-04/SP Datasheet - Page 29

• Manufacturer Part Number: PIC16C73A-04/SP
• Description: 28 PIN, 7 KB OTP, 192 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16C73A-04/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 4 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2.5-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 4-3:
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch-
10Fh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch-
18Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
Address
Bank 2
1997 Microchip Technology Inc.
Bank 3
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(1,4)
(4)
(1,4)
(4)
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD and PORTE are not physically implemented on the PIC16C76, read as ‘0’.
Shaded locations are unimplemented, read as ‘0’.
tents are transferred to the upper byte of the program counter.
Name
INDF
TMR0
PCL
STATUS
FSR
PORTB
PCLATH
INTCON
INDF
OPTION
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
—
—
—
—
—
—
—
—
—
—
PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
Unimplemented
PORTB Data Latch when written: PORTB pins when read
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
Unimplemented
PORTB Data Direction Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
RBPU
Bit 7
IRP
GIE
IRP
GIE
—
—
INTEDG
Bit 6
PEIE
PEIE
RP1
RP1
—
—
T0CS
Bit 5
T0IE
T0IE
RP0
RP0
—
—
Write Buffer for the upper 5 bits of the Program Counter
Write Buffer for the upper 5 bits of the Program Counter
T0SE
Bit 4
INTE
INTE
TO
TO
RBIE
RBIE
Bit 3
PSA
PD
PD
Bit 2
T0IF
T0IF
PS2
Z
Z
Bit 1
INTF
INTF
PS1
DC
DC
PIC16C7X
Bit 0
RBIF
RBIF
PS0
C
C
DS30390E-page 29
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---0 0000 ---0 0000
0000 000x 0000 000u
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
---0 0000 ---0 0000
0000 000x 0000 000u
Value on:
POR,
BOR
—
—
—
—
—
—
—
—
—
—
other resets
Value on all
(2)
—
—
—
—
—
—
—
—
—
—