74HC107N,652 Philips Semiconductors, 74HC107N,652 Datasheet

74HC107N,652

Manufacturer Part Number

74HC107N,652

Description

DUAL J-K F/F W/NEG-EDGE TRIG

Manufacturer

Philips Semiconductors

Datasheet

1.74HC107N652.pdf (2 pages)

Specifications of 74HC107N,652

Circuit Type

Low-Power Schottky, Silicon Gate, Standard

Function Type

4-Inputs

Logic Function

Flip-Flop

Logic Type

CMOS

Number Of Circuits

Dual

Package Type

DIP-14

Special Features

J-K, Negative-Edge-Triggered

Temperature, Operating, Range

-40 to +125 °C

Voltage, Supply

4.5 V

Lead Free Status / Rohs Status

RoHS Compliant part Electrostatic Device

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Philips Semiconductors

FEATURES

GENERAL DESCRIPTION

The 74HC/HCT107 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; T

Notes

1. C

2. For HC the condition is V

ORDERING INFORMATION

See

PHL

max

Output capability: standard

Dual JK ﬂip-ﬂop with reset; negative-edge trigger

For HCT the condition is V

“74HC/HCT/HCU/HCMOS Logic Package Information”

/ t

SYMBOL

= input frequency in MHz

category: flip-flops

= output frequency in MHz

PLH

= output load capacitance in pF

= supply voltage in V

is used to determine the dynamic power dissipation (P

= C

amb

= 25 C; t

propagation delay

maximum clock frequency

input capacitance

power dissipation

) = sum of outputs

capacitance per ﬂip-ﬂop

nCP to nQ

nR to nQ, nQ

= t

PARAMETER

= GND to V

= 6 ns

) where:

1.5 V.

notes 1 and 2

= 15 pF;

= 5 V

CONDITIONS

The 74HC/HCT107 are dual negative-edge triggered

JK-type flip-flops featuring individual J, K, clock (nCP) and

reset (nR) inputs; also complementary Q and Q outputs.

The J and K inputs must be stable one set-up time prior to

the HIGH-to-LOW clock transition for predictable

operation.

The reset (nR) is an asynchronous active LOW input.

When LOW, it overrides the clock and data inputs, forcing

the Q output LOW and the Q output HIGH.

Schmitt-trigger action in the clock input makes the circuit

highly tolerant to slower clock rise and fall times.

in W):

3.5

TYPICAL

74HC/HCT107

Product speciﬁcation

3.5

HCT

MHz

UNIT

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74HC107N,652 Summary of contents

Page 1

... Philips Semiconductors Dual JK ﬂip-ﬂop with reset; negative-edge trigger FEATURES Output capability: standard I category: flip-flops CC GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. ...

Page 2

... Philips Semiconductors Dual JK ﬂip-ﬂop with reset; negative-edge trigger DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications” Output capability: standard I category: flip-flops CC AC CHARACTERISTICS FOR 74HC GND = ns SYMBOL PARAMETER propagation delay PHL PLH nCP to nQ propagation delay ...

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