DSPIC33FJ256GP710-I/PT Microchip Technology Inc., DSPIC33FJ256GP710-I/PT Datasheet - Page 276

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DSPIC33FJ256GP710-I/PT

Manufacturer Part Number
DSPIC33FJ256GP710-I/PT
Description
DSP, 16-Bit, 256KB Flash, 30KB RAM, 85 I/O, TQFP-100
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet

Specifications of DSPIC33FJ256GP710-I/PT

A/d Inputs
32-Channels, 12-Bit
Comparators
8
Cpu Speed
40 MIPS
Eeprom Memory
0 Bytes
Input Output
85
Interface
CAN, I2C, SPI, UART/USART
Ios
85
Memory Type
Flash
Number Of Bits
16
Package Type
100-pin TQFP
Programmable Memory
256K Bytes
Ram Size
30K Bytes
Timers
9-16-bit, 4-32-bit
Voltage, Range
3-3.6
Lead Free Status / Rohs Status
RoHS Compliant part

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dsPIC33F
REGISTER 21-5:
REGISTER 21-6:
DS70165E-page 274
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
RSE15
TSE15
R/W-0
R/W-0
R/W-0
R/W-0
RSE7
TSE7
RSE<15:0>: Receive Slot Enable bits
1 = CSDI data is received during the individual time slot n
0 = CSDI data is ignored during the individual time slot n
TSE<15:0>: Transmit Slot Enable Control bits
1 = Transmit buffer contents are sent during the individual time slot n
0 = CSDO pin is tri-stated or driven to logic ‘0’, during the individual time slot, depending on the state
RSE14
TSE14
R/W-0
R/W-0
R/W-0
R/W-0
RSE6
TSE6
of the CSDOM bit
RSCON: DCI RECEIVE SLOT CONTROL REGISTER
TSCON: DCI TRANSMIT SLOT CONTROL REGISTER
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
RSE13
TSE13
R/W-0
R/W-0
R/W-0
R/W-0
RSE5
TSE5
RSE12
TSE12
R/W-0
R/W-0
R/W-0
R/W-0
RSE4
TSE4
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RSE11
TSE11
R/W-0
R/W-0
R/W-0
R/W-0
RSE3
TSE3
RSE10
TSE10
R/W-0
R/W-0
R/W-0
R/W-0
RSE2
TSE2
© 2007 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
RSE9
RSE1
TSE9
TSE1
R/W-0
R/W-0
R/W-0
R/W-0
RSE8
RSE0
TSE8
TSE0
bit 8
bit 0
bit 8
bit 0

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