PIC16F873A-I/SP Microchip Technology Inc., PIC16F873A-I/SP Datasheet - Page 47
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PIC16F873A-I/SP
Manufacturer Part Number
PIC16F873A-I/SP
Description
28 PIN, 7 KB FLASH, 192 RAM, 22 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F873A-ISP.pdf
(218 pages)
Specifications of PIC16F873A-I/SP
A/d Inputs
5-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
128 Bytes
Input Output
22
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
7K Bytes
Ram Size
192 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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At the completion of the write cycle, the WR bit is
cleared and the EEIF interrupt flag bit is set. (EEIF
must be cleared by firmware.) Since the microcontroller
does not execute instructions during the write cycle, the
firmware does not necessarily have to check either
EEIF, or WR, to determine if the write had finished.
EXAMPLE 4-4:
4.6
The PIC16F87X devices do not automatically verify the
value written during a write operation. Depending on
the application, good programming practice may dic-
tate that the value written to memory be verified against
the original value. This should be used in applications
where excessive writes can stress bits near the speci-
fied endurance limits.
BSF
BCF
MOVF
MOVWF
MOVF
MOVWF
MOVF
MOVWF
MOVF
MOVWF
BSF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
BSF
BCF
2001 Microchip Technology Inc.
EECON1, EEPGD ;Point to Program memory
Write Verify
STATUS, RP1
STATUS, RP0
ADDRL, W
EEADR
ADDRH, W
EEADRH
VALUEL, W
EEDATA
VALUEH, W
EEDATH
STATUS, RP0
EECON1, WREN
INTCON, GIE
0x55
EECON2
0xAA
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
FLASH PROGRAM WRITE
;Only disable interrupts
;Two NOPs to allow micro
;
;Bank 2
;Write address
;of desired
;program memory
;location
;Write value to
;program at
;desired memory
;location
;Bank 3
;Enable writes
;if already enabled,
;otherwise discard
;Write 55h to
;EECON2
;Write AAh to
;EECON2
;Start write operation
;to setup for write
;Only enable interrupts
;if using interrupts,
;otherwise discard
;Disable writes
4.7
There are conditions when the device may not want to
write to the EEPROM data memory or FLASH program
memory. To protect against these spurious write condi-
tions, various mechanisms have been built into the
PIC16F87X devices. On power-up, the WREN bit is
cleared and the Power-up Timer (if enabled) prevents
writes.
The write initiate sequence, and the WREN bit
together, help prevent any accidental writes during
brown-out, power glitches, or firmware malfunction.
4.8
The PIC16F87X devices have two code protect mecha-
nisms, one bit for EEPROM data memory and two bits for
FLASH program memory. Data can be read and written
to the EEPROM data memory, regardless of the state of
the code protection bit, CPD. When code protection is
enabled and CPD cleared, external access via ICSP is
disabled, regardless of the state of the program memory
code protect bits. This prevents the contents of EEPROM
data memory from being read out of the device.
The state of the program memory code protect bits,
CP0 and CP1, do not affect the execution of instruc-
tions out of program memory. The PIC16F87X devices
can always read the values in program memory,
regardless of the state of the code protect bits. How-
ever, the state of the code protect bits and the WRT bit
will have different effects on writing to program mem-
ory. Table 4-1 shows the effect of the code protect bits
and the WRT bit on program memory.
Once code protection has been enabled for either
EEPROM data memory or FLASH program memory,
only a full erase of the entire device will disable code
protection.
Protection Against Spurious
Writes
Operation While Code Protected
PIC16F87X
DS30292C-page 45