DSPIC33FJ64MC506-I/PT Microchip Technology Inc., DSPIC33FJ64MC506-I/PT Datasheet - Page 258
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
DSPIC33FJ64MC506-I/PT
Manufacturer Part Number
DSPIC33FJ64MC506-I/PT
Description
DSP, 16-Bit, 64KB Flash, 8KB RAM, 53 I/O, TQFP-64
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC33FJ64MC506-IPT.pdf
(370 pages)
Specifications of DSPIC33FJ64MC506-I/PT
A/d Inputs
16-Channels, 12-Bit
Comparators
8
Cpu Speed
40 MIPS
Eeprom Memory
0 Bytes
Input Output
53
Interface
CAN, I2C, SPI, UART/USART
Ios
53
Memory Type
Flash
Number Of Bits
16
Package Type
64-pin TQFP
Programmable Memory
64K Bytes
Ram Size
8K Bytes
Timers
9-16-bit, 4-32-bit
Voltage, Range
3-3.6
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ64MC506-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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dsPIC33F
REGISTER 20-25:
DS70165E-page 256
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
Note 1:
TXENm
TXENn
R/W-0
R/W-0
This bit is cleared when TXREQ is set.
See Definition for Bits 7-0, Controls Buffer n
TXENm: TX/RX Buffer Selection bit
1 = Buffer TRBn is a transmit buffer
0 = Buffer TRBn is a receive buffer
TXABTm: Message Aborted bit
1 = Message was aborted
0 = Message completed transmission successfully
TXLARBm: Message Lost Arbitration bit
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
TXERRm: Error Detected During Transmission bit
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
TXREQm: Message Send Request bit
Setting this bit to ‘
is successfully sent. Clearing the bit to ‘
RTRENm: Auto-Remote Transmit Enable bit
1 = When a remote transmit is received, TXREQ will be set
0 = When a remote transmit is received, TXREQ will be unaffected
TXmPRI<1:0>: Message Transmission Priority bits
11 = Highest message priority
10 = High intermediate message priority
01 = Low intermediate message priority
00 = Lowest message priority
TXABTm
TXABTn
R-0
R-0
CiTRmnCON: ECAN TX/RX BUFFER m CONTROL REGISTER (m = 0,2,4,6; n = 1,3,5,7)
(1)
W = Writable bit
TXLARBm
‘1’ = Bit is set
TXLARBn
1
’ requests sending a message. The bit will automatically clear when the message
R-0
R-0
(1)
TXERRm
TXERRn
(1)
R-0
R-0
Preliminary
(1)
0
’ while set will request a message abort.
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TXREQm
TXREQn
R/W-0
R/W-0
(1)
RTRENm
RTRENn
R/W-0
R/W-0
© 2007 Microchip Technology Inc.
x = Bit is unknown
R/W-0
R/W-0
TXmPRI<1:0>
TXnPRI<1:0>
R/W-0
R/W-0
bit 8
bit 0
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