PIC12C508A-04I/P Microchip Technology Inc., PIC12C508A-04I/P Datasheet - Page 40
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC12C508A-04I/P
Manufacturer Part Number
PIC12C508A-04I/P
Description
8 PIN, 0.75 KB OTP, 25 RAM, 6 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC12C508A-04IP.pdf
(113 pages)
Specifications of PIC12C508A-04I/P
Cpu Speed
1 MIPS
Eeprom Memory
0 Bytes
Input Output
5
Memory Type
OTP
Number Of Bits
8
Package Type
8-pin PDIP
Programmable Memory
768 Bytes
Ram Size
25 Bytes
Speed
4 MHz
Timers
1-8-bit
Voltage, Range
2.5-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12C508A-04I/P
Manufacturer:
MAXIM
Quantity:
731
Part Number:
PIC12C508A-04I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC12C508A-04I/PVAO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC12C5XX
8.3.1
This configuration bit when unprogrammed (left in the
‘1’ state) enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
V
Figure 8-7. When pin GP3/MCLR/V
MCLR, the internal pull-up is always on.
FIGURE 8-7:
8.4
The PIC12C5XX family incorporates on-chip Power-
On Reset (POR) circuitry which provides an internal
chip reset for most power-up situations.
The on-chip POR circuit holds the chip in reset until
V
tion. To take advantage of the internal POR, program
the GP3/MCLR/V
resistor to V
weak pull-up resistor is implemented using a transistor.
Refer to Table 11-1 for the pull-up resistor ranges. This
will eliminate external RC components usually needed
to create a Power-on Reset. A maximum rise time for
V
details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating parameters are
met.
A simplified block diagram of the on-chip Power-On
Reset circuit is shown in Figure 8-8.
DS40139E-page 40
DD
DD
DD
, and the pin is assigned to be a GPIO. See
has reached a high enough level for proper opera-
is specified. See Electrical Specifications for
MCLR ENABLE
Power-On Reset (POR)
GP3/MCLR/V
DD
or program the pin as GP3. An internal
WEAK
PULL-UP
PP
MCLR SELECT
PP
pin as MCLR and tie through a
MCLRE
PP
is configured as
INTERNAL MCLR
The Power-On Reset circuit and the Device Reset
Timer (Section 8.5) circuit are closely related. On
power-up, the reset latch is set and the DRT is reset.
The DRT timer begins counting once it detects MCLR
to be high. After the time-out period, which is typically
18 ms, it will reset the reset latch and thus end the on-
chip reset signal.
A power-up example where MCLR is held low is
shown in Figure 8-9. V
stabilize before bringing MCLR high. The chip will
actually come out of reset T
goes high.
In Figure 8-10, the on-chip Power-On Reset feature is
being used (MCLR and V
pin is programmed to be GP3.). The V
before the start-up timer times out and there is no
problem in getting a proper reset. However, Figure 8-
11 depicts a problem situation where V
slowly. The time between when the DRT senses that
MCLR is high and when MCLR (and V
reach their full value, is too long. In this situation, when
the start-up timer times out, V
V
guaranteed to function correctly. For such situations,
we recommend that external RC circuits be used to
achieve longer POR delay times (Figure 8-10).
For additional information refer to Application Notes
“ Power-Up Considerations” - AN522 and “ Power-up
Trouble Shooting ” - AN607.
DD
Note:
(min) value and the chip is, therefore, not
When the device starts normal operation
(exits the reset condition), device operating
parameters (voltage, frequency, tempera-
ture, etc.) must be meet to ensure opera-
tion. If these conditions are not met, the
device must be held in reset until the oper-
ating conditions are met.
DD
1999 Microchip Technology Inc.
DD
is allowed to rise and
are tied together or the
DD
DRT
has not reached the
msec after MCLR
DD
DD
DD
) actually
rises too
is stable