PIC12F675-E/P Microchip Technology Inc., PIC12F675-E/P Datasheet - Page 43

• Manufacturer Part Number: PIC12F675-E/P
• Description: 8 PIN, 1.75 KB FLASH, 64 RAM, 6 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F675-E/P

• A/d Inputs: 4-Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 5
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin PDIP
• Programmable Memory: 1.75K Bytes
• Ram Size: 64 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

7.0
The analog-to-digital converter (A/D) allows conversion
of an analog input signal to a 10-bit binary representa-
tion of that signal. The PIC12F675 has four analog
inputs, multiplexed into one sample and hold circuit.
FIGURE 7-1:
7.1
There are two registers available to control the
functionality of the A/D module:
1.
2.
7.1.1
The ANS3:ANS0 bits (ANSEL<3:0>) and the TRISIO
bits control the operation of the A/D port pins. Set the
corresponding TRISIO bits to set the pin output driver
to its high impedance state. Likewise, set the
corresponding ANS bit to disable the digital input
buffer.
7.1.2
There are four analog channels on the PIC12F675,
AN0
(ADCON0<3:2>) control which channel is connected to
the sample and hold circuit.
7.1.3
There are two options for the voltage reference to the
A/D converter: either V
applied to V
 2003 Microchip Technology Inc.
Note:
ADCON0 (Register 7-1)
ANSEL (Register 7-2)
through
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
(PIC12F675 ONLY)
A/D Configuration and Operation
Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
ANALOG PORT PINS
CHANNEL SELECTION
VOLTAGE REFERENCE
REF
GP1/AN1/V
is used. The VCFG bit (ADCON0<6>)
GP0/AN0
GP2/AN2
GP4/AN3
AN3.
REF
A/D BLOCK DIAGRAM
DD
is used, or an analog voltage
CHS1:CHS0
The
V
CHS1:CHS0
REF
V
DD
GO/DONE
VCFG = 0
VCFG = 1
bits
ADON
V
SS
ADC
The output of the sample and hold is connected to the
input of the converter. The converter generates a
binary result via successive approximation and stores
the result in a 10-bit register. The voltage reference
used in the conversion is software selectable to either
V
shows the block diagram of the A/D on the PIC12F675.
controls the voltage reference selection. If VCFG is set,
then the voltage on the V
otherwise, V
7.1.4
The A/D conversion cycle requires 11 T
of the conversion clock is software selectable via the
ADCS bits (ANSEL<6:4>). There are seven possible
clock options:
• F
• F
• F
• F
• F
• F
• F
For correct conversion, the A/D conversion clock
(1/T
1.6 µs. Table 7-1 shows a few T
selected frequencies.
DD
OSC
OSC
OSC
OSC
OSC
OSC
RC
AD
or a voltage applied by the V
ADFM
) must be selected to ensure a minimum T
(dedicated internal RC oscillator)
/2
/4
/8
/16
/32
/64
ADRESH ADRESL
CONVERSION CLOCK
DD
PIC12F629/675
is the reference.
10
10
REF
pin is the reference;
AD
REF
DS41190C-page 41
calculations for
AD
pin. Figure 7-1
. The source
AD
of