PIC10F200-I/P Microchip Technology Inc., PIC10F200-I/P Datasheet - Page 48

• Manufacturer Part Number: PIC10F200-I/P
• Description: 8 PIN, 384 B FLASH, 16 RAM, 4 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC10F200-I/P

• Cpu Speed: 1 MIPS
• Eeprom Memory: 0 Bytes
• Frequency: 4 MHz
• Input Output: 4
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin PDIP
• Programmable Memory: 375 Bytes
• Ram Size: 16 Bytes
• Speed: 4 MHz
• Timers: 1-8-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC10F200/202/204/206
9.5
On the PIC10F200/202/204/206 devices, the DRT runs
any time the device is powered up.
The DRT operates on an internal oscillator. The
processor is kept in Reset as long as the DRT is active.
The DRT delay allows V
for the oscillator to stabilize.
The on-chip DRT keeps the devices in a Reset
condition for approximately 18 ms after MCLR has
reached a logic high (V
GP3/MCLR/V
network connected to the MCLR input is not required in
most cases. This allows savings in cost-sensitive and/
or space restricted applications, as well as allowing the
use of the GP3/MCLR/V
input.
The Device Reset Time delays will vary from chip-to-
chip due to V
See AC parameters for details.
Reset sources are POR, MCLR, WDT time-out and
wake-up on pin change. See Section 9.9.2 “Wake-up
from Sleep”, Notes 1, 2 and 3.
TABLE 9-3:
9.6
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator, which does not require any external
components. This RC oscillator is separate from the
internal 4 MHz oscillator. This means that the WDT will
run even if the main processor clock has been stopped,
for example, by execution of a SLEEP instruction.
During normal operation or Sleep, a WDT Reset or
wake-up Reset, generates a device Reset.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer Reset.
The WDT can be permanently disabled by program-
ming the configuration WDTE as a ‘0’ (see Section 9.1
“Configuration Bits”). Refer to the PIC10F200/202/
204/206 Programming Specifications to determine how
to access the Configuration Word.
DS41239C-page 46
INTOSC
Oscillator
Device Reset Timer (DRT)
Watchdog Timer (WDT)
PP
DD
, temperature and process variation.
as MCLR and using an external RC
DRT (DEVICE RESET TIMER
PERIOD)
18 ms (typical)
POR Reset
IH
DD
PP
MCLR) level. Programming
to rise above V
pin as a general purpose
10 s (typical)
Subsequent
Resets
DD
min. and
Preliminary
9.6.1
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by
writing to the OPTION register. Thus, a time-out period
of a nominal 2.3 seconds can be realized. These peri-
ods vary with temperature, V
process variations (see DC specs).
Under worst-case conditions (V
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
9.6.2
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device Reset.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake-up Reset.
WDT PERIOD
WDT PROGRAMMING
CONSIDERATIONS
© 2006 Microchip Technology Inc.
DD
DD
= Min., Temperature
and part-to-part