DSPIC33FJ256GP710-I/PF Microchip Technology Inc., DSPIC33FJ256GP710-I/PF Datasheet - Page 146
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DSPIC33FJ256GP710-I/PF
Manufacturer Part Number
DSPIC33FJ256GP710-I/PF
Description
16 BIT MCU/DSP 100LD 40MIPS 256KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC33FJ256GP710-IPF.pdf
(371 pages)
Specifications of DSPIC33FJ256GP710-I/PF
A/d Inputs
32-Channels, 12-Bit
Comparators
8
Cpu Speed
40 MIPS
Eeprom Memory
0 Bytes
Input Output
85
Interface
CAN/I2C/SPI/UART
Ios
85
Memory Type
Flash
Number Of Bits
16
Package Type
100-pin TQFP
Programmable Memory
256K Bytes
Ram Size
30K Bytes
Timers
9-16-bit, 4-32-bit
Voltage, Range
3-3.6
Lead Free Status / Rohs Status
RoHS Compliant part
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- Current page: 146 of 371
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dsPIC33F
REGISTER 7-7:
DS70165D-page 144
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
PWCOL7
XWCOL7
R/C-0
R/C-0
PWCOL7: Channel 7 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
PWCOL6: Channel 6 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
PWCOL5: Channel 5 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
PWCOL4: Channel 4 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
PWCOL3: Channel 3 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
PWCOL2: Channel 2 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
PWCOL1: Channel 1 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
PWCOL0: Channel 0 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
XWCOL7: Channel 7 DMA RAM Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
XWCOL6: Channel 6 DMA RAM Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
XWCOL5: Channel 5 DMA RAM Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
XWCOL4: Channel 4 DMA RAM Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
PWCOL6
XWCOL6
R/C-0
R/C-0
DMACS0: DMA CONTROLLER STATUS REGISTER 0
W = Writable bit
‘1’ = Bit is set
PWCOL5
XWCOL5
R/C-0
R/C-0
PWCOL4
XWCOL4
R/C-0
R/C-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PWCOL3
XWCOL3
R/C-0
R/C-0
PWCOL2
XWCOL2
R/C-0
R/C-0
© 2006 Microchip Technology Inc.
x = Bit is unknown
PWCOL1
XWCOL1
R/C-0
R/C-0
PWCOL0
XWCOL0
R/C-0
R/C-0
bit 8
bit 0
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