PIC18F4620-I/PT Microchip Technology Inc., PIC18F4620-I/PT Datasheet - Page 379

• Manufacturer Part Number: PIC18F4620-I/PT
• Description: 44 Pin, 64 KB Flash, 3968 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4620-I/PT

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 36
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 4K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Data EEPROM Memory ..................................................... 83
Data Memory ..................................................................... 59
DAW ................................................................................. 286
DC and AC Characteristics
DC Characteristics ........................................................... 336
DCFSNZ .......................................................................... 287
DECF ............................................................................... 286
DECFSZ ........................................................................... 287
Demonstration Boards
Development Support ...................................................... 317
Device Differences ........................................................... 371
Device Overview .................................................................. 7
Device Reset Timers .......................................................... 45
Direct Addressing ............................................................... 68
E
Effect on Standard PIC Instructions ................................. 314
Effects of Power Managed Modes on
Electrical Characteristics .................................................. 323
Enhanced Capture/Compare/PWM (ECCP) .................... 147
Enhanced PWM Mode. See PWM (ECCP Module).
 2004 Microchip Technology Inc.
Associated Registers ................................................. 87
EEADR and EEADRH Registers ............................... 83
EECON1 and EECON2 Registers ............................. 83
Operation During Code-Protect ................................. 86
Protection Against Spurious Write ............................. 86
Reading ...................................................................... 85
Using .......................................................................... 86
Write Verify ................................................................ 85
Writing ........................................................................ 85
Access Bank .............................................................. 61
and the Extended Instruction Set ............................... 69
Bank Select Register (BSR) ....................................... 59
General Purpose Registers ........................................ 61
Map for PIC18FX525/X620 ........................................ 60
Special Function Registers ........................................ 62
Graphs and Tables .................................................. 361
Power-Down and Supply Current ............................ 327
Supply Voltage ......................................................... 326
PICDEM 1 ................................................................ 320
PICDEM 17 .............................................................. 321
PICDEM 18R ........................................................... 321
PICDEM 2 Plus ........................................................ 320
PICDEM 3 ................................................................ 320
PICDEM 4 ................................................................ 320
PICDEM LIN ............................................................ 321
PICDEM USB ........................................................... 321
PICDEM.net Internet/Ethernet ................................. 320
Details on Individual Family Members ......................... 8
Features (table) ............................................................ 9
New Core Features ...................................................... 7
Other Special Features ................................................ 8
Oscillator Start-up Timer (OST) ................................. 45
PLL Lock Time-out ..................................................... 45
Power-up Timer (PWRT) ........................................... 45
Time-out Sequence .................................................... 45
Various Clock Sources ............................................... 31
Associated Registers ............................................... 160
Capture and Compare Modes .................................. 148
Capture Mode. See Capture (ECCP Module).
Outputs and Configuration ....................................... 148
Pin Configurations for ECCP1 ................................. 148
PWM Mode. See PWM (ECCP Module).
Standard PWM Mode ............................................... 148
Timer Resources ...................................................... 148
PIC18F2525/2620/4525/4620
Preliminary
Enhanced Universal Synchronous A
Equations
Errata ................................................................................... 5
EUSART
Evaluation and Programming Tools ................................. 321
Extended Instruction Set
External Clock Input ........................................................... 24
F
Fail-Safe Clock Monitor ........................................... 249, 261
Fast Register Stack ........................................................... 56
Firmware Instructions ...................................................... 267
synchronous Receiver Transmitter (EUSART).
See EUSART.
A/D Acquisition Time ............................................... 228
A/D Minimum Charging Time .................................. 228
Asynchronous Mode ................................................ 211
Baud Rate Generator
Baud Rate Generator (BRG) ................................... 205
Synchronous Master Mode ...................................... 217
Synchronous Slave Mode ........................................ 220
ADDFSR .................................................................. 310
ADDULNK ............................................................... 310
and Using MPLAB Tools ......................................... 316
CALLW .................................................................... 311
Considerations for Use ............................................ 314
MOVSF .................................................................... 311
MOVSS .................................................................... 312
PUSHL ..................................................................... 312
SUBFSR .................................................................. 313
SUBULNK ................................................................ 313
Syntax ...................................................................... 309
Exiting Operation ..................................................... 261
Interrupts in Power Managed Modes ....................... 262
POR or Wake from Sleep ........................................ 262
WDT During Oscillator Failure ................................. 261
12-Bit Break Transmit and Receive ................. 216
Associated Registers, Receive ........................ 214
Associated Registers, Transmit ....................... 212
Auto-Wake-up on Sync Break ......................... 214
Receiver .......................................................... 213
Setting up 9-Bit Mode with
Transmitter ...................................................... 211
Operation in Power
Associated Registers ....................................... 206
Auto-Baud Rate Detect .................................... 209
Baud Rate Error, Calculating ........................... 206
Baud Rates, Asynchronous Modes ................. 207
High Baud Rate Select (BRGH Bit) ................. 205
Sampling ......................................................... 205
Associated Registers, Receive ........................ 219
Associated Registers, Transmit ....................... 218
Reception ........................................................ 219
Transmission ................................................... 217
Associated Registers, Receive ........................ 221
Associated Registers, Transmit ....................... 220
Reception ........................................................ 221
Transmission ................................................... 220
Address Detect ........................................ 213
Managed Mode ....................................... 205
DS39626B-page 377