PIC18F4550-I/PT Microchip Technology Inc., PIC18F4550-I/PT Datasheet - Page 13

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PIC18F4550-I/PT

Manufacturer Part Number
PIC18F4550-I/PT
Description
44 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F4550-I/PT

A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
12 MIPS
Eeprom Memory
256 Bytes
Input Output
34
Interface
I2C/SPI/UART/USART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin TQFP
Programmable Memory
32K Bytes
Ram Size
2K Bytes
Speed
48 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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FIGURE 1-2:
© 2006 Microchip Technology Inc.
V
OSC1
OSC2
T1OSI
T1OSO
ICPGC
ICPGD
ICPORTS
ICRST
MCLR
V
Note 1:
Comparator
DD
USB
HLVD
BOR
, V
Instruction Bus <16>
(1)
2:
3:
4:
Program Memory
(2)
(2)
SS
Table Pointer<21>
(3)
(3)
(3)
Address Latch
(24/32 Kbytes)
Data Latch
inc/dec logic
(3)
RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer
to Section 2.0 “Oscillator Configurations” for additional information.
These pins are only available on 44-pin TQFP packages under certain conditions. Refer to Section 25.9 “Special ICPORT Features
(Designated Packages Only)” for additional information.
RB3 is the alternate pin for CCP2 multiplexing.
21
EEPROM
ECCP1
Data
Single-Supply
Programming
Debugger
Oscillator
Oscillator
Oscillator
In-Circuit
Internal
INTRC
20
8
8 MHz
Block
PIC18F4455/4550 (40/44-PIN) BLOCK DIAGRAM
ROM Latch
Table Latch
Instruction
Decode &
USB Voltage
Control
Timer0
PCLATU
Regulator
PCU
CCP2
Program Counter
IR
31 Level Stack
STKPTR
PCH
PCLATH
Start-up Timer
Clock Monitor
Brown-out
Watchdog
Power-up
Power-on
Oscillator
Fail-Safe
8
Reset
Reset
State Machine
Control Signals
Timer
Timer
PCL
Timer1
MSSP
Data Bus<8>
8
PIC18F2455/2550/4455/4550
EUSART
Timer2
Preliminary
Reference
Band Gap
BITOP
BSR
4
3
8
Data Address<12>
Address
Decode
inc/dec
Address Latch
FSR0
FSR1
FSR2
Data Memory
logic
Data Latch
(2 Kbytes)
PRODH
8
ALU<8>
8 x 8 Multiply
12
Timer3
10-Bit
ADC
W
8
12
Access
8
Bank
PRODL
4
12
8
8
8
8
USB
PORTB
PORTD
PORTE
PORTA
PORTC
RA0/AN0
RA1/AN1
RA2/AN2/V
RA3/AN3/V
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
OSC2/CLKO/RA6
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2
RB4/AN11/KBI0/CSSPP
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
RD0/SPP0:RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
MCLR/V
PP
DS39632C-page 11
/RE3
REF
REF
-/CV
+
(1)
(4)
(4)
/VPO
REF
/UOE

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