PIC18F4520-I/PT Microchip Technology Inc., PIC18F4520-I/PT Datasheet - Page 277

• Manufacturer Part Number: PIC18F4520-I/PT
• Description: 44 Pin, 32 KB Flash, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4520-I/PT

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

ANDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2004 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
REG
W
REG
Q1
=
=
=
=
register ‘f’
AND W with f
ANDWF
0
d
a
(W) .AND. (f)
N, Z
The contents of W are AND’ed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
ANDWF
Read
0001
Q2
17h
C2h
02h
C2h
f
[0,1]
[0,1]
255
f {,d {,a}}
01da
REG, 0, 0
Process
Data
dest
Q3
95 (5Fh). See
ffff
destination
PIC18F2420/2520/4420/4520
Write to
Q4
ffff
Preliminary
BC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If CARRY
If CARRY
Q1
No
Q1
PC
PC
Read literal
Read literal
operation
Branch if Carry
BC
-128
if CARRY bit is ‘1’
(PC) + 2 + 2n
None
If the CARRY bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
Q2
Q2
No
‘n’
‘n’
=
=
=
=
=
n
n
address (HERE)
1;
address (HERE + 12)
0;
address (HERE + 2)
127
0010
BC
operation
Process
Process
Data
Data
PC
Q3
No
Q3
DS39631A-page 275
5
nnnn
Write to PC
operation
operation
Q4
No
Q4
No
nnnn