MCP2515-I/SO Microchip Technology Inc., MCP2515-I/SO Datasheet - Page 24

• Manufacturer Part Number: MCP2515-I/SO
• Description: CAN CONTROLLER WITH SPI INTERFACE
• Manufacturer: Microchip Technology Inc.
• Type: Programmable Peripheral Interfacer

Specifications of MCP2515-I/SO

• Package Type: 18-Pin SOIC
• Voltage, Supply: 2.7-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

MCP2515
4.3
If enabled, the Start-Of-Frame signal is generated on
the SOF pin at the beginning of each CAN message
detected on the RXCAN pin.
The RXCAN pin monitors an idle bus for a recessive-
to-dominant edge. If the dominant condition remains
until the sample point, the MCP2515 interprets this as
a SOF and a SOF pulse is generated. If the dominant
condition does not remain until the sample point, the
MCP2515 interprets this as a glitch on the bus and no
SOF signal is generated. Figure 4-1 illustrates SOF
signalling and glitch-filtering.
As with One-shot mode, one use for SOF signaling is
for TTCAN-type systems. In addition, by monitoring
both the RXCAN pin and the SOF pin, a MCU can
detect early physical bus problems by detecting small
glitches before they affect the CAN communications.
4.4
In addition to the INT pin, which provides an interrupt
signal to the MCU for many different conditions, the
receive buffer full pins (RX0BF and RX1BF) can be
used to indicate that a valid message has been loaded
into RXB0 or RXB1, respectively. The pins have three
different configurations (Register 4-1):
1.
2.
3.
FIGURE 4-1:
DS21801D-page 24
Disabled.
Buffer Full Interrupt.
Digital Output.
Start-of-Frame Signal
RX0BF and RX1BF Pins
RXCAN
RXCAN
Normal SOF Signaling
Glitch-Filtering
SOF
SOF
START-OF-FRAME SIGNALING
EXPECTED START-OF-FRAME BIT
START-OF-FRAME BIT
Expected
Preliminary
Sample
Point
Sample
Point
4.4.1
The RXBnBF pins can be disabled to the high-
impedance state by clearing BFPCTRL.BnBFE.
4.4.2
The RXBnBF pins can be configured to act as either
buffer full interrupt pins or as standard digital outputs.
Configuration and status of these pins is available via
the BFPCTRL register (Register 4-3). When set to
operate in Interrupt mode (by setting BFPCTRL.BxBFE
and BFPCTRL.BxBFM bits), these pins are active-low
and are mapped to the CANINTF.RXnIF bit for each
receive buffer. When this bit goes high for one of the
receive buffers (indicating that a valid message has
been loaded into the buffer), the corresponding
RXBnBF pin will go low. When the CANINTF.RXnIF bit
is cleared by the MCU, the corresponding interrupt pin
will go to the logic-high state until the next message is
loaded into the receive buffer.
DISABLED
CONFIGURED AS BUFFER FULL
BUS IDLE
© 2005 Microchip Technology Inc.
ID BIT