PIC18F452-I/PT Microchip Technology Inc., PIC18F452-I/PT Datasheet - Page 93

• Manufacturer Part Number: PIC18F452-I/PT
• Description: 44 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F452-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 9-5:
FIGURE 9-6:
© 2006 Microchip Technology Inc.
Note 1:
Note 1:
2:
2:
3:
I/O pins have diode protection to V
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
CCP Output
CCP2 Input
I/O pin has diode protection to V
To enable weak pull-ups, set the appropriate DDR bit(s) and clear the RBPU bit (INTCON2<7>).
The CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (=’0’) in the configuration register.
RD PORTB
Enable
CCP Output
WR LATB or
WR PORTB
WR TRISB
RBPU
Data Bus
BLOCK DIAGRAM OF RB2:RB0 PINS
BLOCK DIAGRAM OF RB3 PIN
(3)
(2)
CCP2MX
(3)
(3)
Data Bus
WR TRIS
WR Port
RB0/INT
RBPU
(2)
Schmitt Trigger
Buffer
RD TRISB
RD PORTB
RD LATB
TRIS Latch
Data Latch
D
D
CK
CK
DD
DD
and V
Q
Q
and V
RD TRIS
RD Port
TRIS Latch
Data Latch
CCP2MX = 0
D
D
CK
CK
SS
SS
.
Schmitt Trigger
Buffer
.
Q
Q
Q
1
0
EN
D
Q
EN
TTL
Input
Buffer
D
V
P
RD Port
DD
Weak
Pull-up
V
I/O pin
V
N
P
SS
DD
(1)
TTL
Input
Buffer
V
P
DD
Weak
Pull-up
PIC18FXX2
I/O pin
(1)
DS39564C-page 91