PIC18F4520-I/P Microchip Technology Inc., PIC18F4520-I/P Datasheet - Page 378

• Manufacturer Part Number: PIC18F4520-I/P
• Description: 40 Pin, 32 KB Flash, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4520-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2420/2520/4420/4520
C
C Compilers
CALL ................................................................................ 282
CALLW ............................................................................. 311
Capture (CCP Module) ..................................................... 141
Capture (ECCP Module) .................................................. 148
Capture/Compare/PWM (CCP) ........................................ 139
Clock Sources .................................................................... 28
CLRF ................................................................................ 283
CLRWDT .......................................................................... 283
Code Examples
Code Protection ............................................................... 249
COMF ............................................................................... 284
Comparator ...................................................................... 233
DS39631A-page 376
MPLAB C17 ............................................................. 318
MPLAB C18 ............................................................. 318
MPLAB C30 ............................................................. 318
Associated Registers ............................................... 143
CCP Pin Configuration ............................................. 141
CCPRxH:CCPRxL Registers ................................... 141
Prescaler .................................................................. 141
Software Interrupt .................................................... 141
Timer1/Timer3 Mode Selection ................................ 141
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................ 140
CCPRxH Register .................................................... 140
CCPRxL Register ..................................................... 140
Compare Mode. See Compare.
Interaction of Two CCP Modules ............................. 140
Module Configuration ............................................... 140
Selecting the 31 kHz Source ...................................... 29
Selection Using OSCCON Register ........................... 29
16 x 16 Signed Multiply Routine ................................ 90
16 x 16 Unsigned Multiply Routine ............................ 90
8 x 8 Signed Multiply Routine .................................... 89
8 x 8 Unsigned Multiply Routine ................................ 89
Changing Between Capture Prescalers ................... 141
Computed GOTO Using an Offset Value ................... 56
Data EEPROM Read ................................................. 85
Data EEPROM Refresh Routine ................................ 86
Data EEPROM Write ................................................. 85
Erasing a Flash Program Memory Row ..................... 78
Fast Register Stack .................................................... 56
How to Clear RAM (Bank 1) Using
Implementing a Real-Time Clock Using
Initializing PORTA .................................................... 105
Initializing PORTB .................................................... 108
Initializing PORTC .................................................... 111
Initializing PORTD .................................................... 114
Initializing PORTE .................................................... 117
Loading the SSPBUF (SSPSR) Register ................. 164
Reading a Flash Program Memory Word .................. 77
Saving Status, WREG and
Writing to Flash Program Memory ....................... 80–81
Analog Input Connection Considerations ................. 237
Associated Registers ............................................... 237
Configuration ............................................................ 234
Effects of a Reset ..................................................... 236
Interrupts .................................................................. 236
Operation ................................................................. 235
Operation During Sleep ........................................... 236
Outputs .................................................................... 235
Indirect Addressing ............................................ 68
a Timer1 Interrupt Service ............................... 131
BSR Registers in RAM ..................................... 103
Preliminary
Comparator Specifications ............................................... 338
Comparator Voltage Reference ....................................... 239
Compare (CCP Module) .................................................. 142
Compare (ECCP Module) ................................................ 148
Computed GOTO ............................................................... 56
Configuration Bits ............................................................ 249
Configuration Register Protection .................................... 266
Context Saving During Interrupts ..................................... 103
Conversion Considerations .............................................. 372
CPFSEQ .......................................................................... 284
CPFSGT .......................................................................... 285
CPFSLT ........................................................................... 285
Crystal Oscillator/Ceramic Resonator ................................ 23
D
Data Addressing Modes .................................................... 68
Data EEPROM
Data EEPROM Memory ..................................................... 83
Data Memory ..................................................................... 59
DAW ................................................................................ 286
DC and AC Characteristics
Reference ................................................................ 235
Response Time ........................................................ 235
Accuracy and Error .................................................. 240
Associated Registers ............................................... 241
Configuring .............................................................. 239
Connection Considerations ...................................... 240
Effects of a Reset .................................................... 240
Operation During Sleep ........................................... 240
Associated Registers ............................................... 143
CCPRx Register ...................................................... 142
Pin Configuration ..................................................... 142
Software Interrupt .................................................... 142
Special Event Trigger .............................. 137, 142, 232
Timer1/Timer3 Mode Selection ................................ 142
Special Event Trigger .............................................. 148
Comparing Addressing Modes with the
Direct ......................................................................... 68
Indexed Literal Offset ................................................ 70
Indirect ....................................................................... 68
Inherent and Literal .................................................... 68
Code Protection ....................................................... 266
Associated Registers ................................................. 87
EEADR Register ........................................................ 83
EECON1 and EECON2 Registers ............................. 83
Operation During Code-Protect ................................. 86
Protection Against Spurious Write ............................. 86
Reading ..................................................................... 85
Using ......................................................................... 86
Write Verify ................................................................ 85
Writing ....................................................................... 85
Access Bank .............................................................. 62
and the Extended Instruction Set .............................. 70
Bank Select Register (BSR) ...................................... 59
General Purpose Registers ....................................... 62
Map for PIC18F2420/4420 ........................................ 60
Map for PIC18F2520/4520 ........................................ 61
Special Function Registers ........................................ 63
Graphs and Tables .................................................. 361
External Signal ................................................ 235
Internal Signal .................................................. 235
Extended Instruction Set Enabled ..................... 71
Instructions Affected .......................................... 70
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