PIC16F74-I/P Microchip Technology Inc., PIC16F74-I/P Datasheet - Page 15

• Manufacturer Part Number: PIC16F74-I/P
• Description: 40 PIN, 7 KB FLASH, 192 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F74-I/P

• A/d Inputs: 8-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 33
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

2.0
There are two memory blocks in each of these
PICmicro
Memory have separate buses so that concurrent
access can occur and is detailed in this section. The
Program Memory can be read internally by user code
(see Section 3.0).
Additional information on device memory may be found
in the PICmicro Mid-Range Reference Manual
(DS33023).
2.1
The PIC16F7X devices have a 13-bit program counter
capable of addressing an 8K word x 14-bit program
memory space. The PIC16F77/76 devices have
8K words of FLASH program memory and the
PIC16F73/74 devices have 4K words. The program
memory maps for PIC16F7X devices are shown in
Figure 2-1. Accessing a location above the physically
implemented address will cause a wraparound.
The RESET Vector is at 0000h and the Interrupt Vector
is at 0004h.
FIGURE 2-1:
 2002 Microchip Technology Inc.
On-Chip
Program
Memory
CALL, RETURN
RETFIE, RETLW
MEMORY ORGANIZATION
Program Memory Organization
®
MCUs. The Program Memory and Data
PIC16F76/77
Interrupt Vector
RESET Vector
Stack Level 8
Stack Level 1
Stack Level 2
PC<12:0>
PROGRAM MEMORY MAPS AND STACKS FOR PIC16F7X DEVICES
Page 0
Page 1
Page 2
Page 3
13
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
17FFh
1800h
1FFFh
2.2
The Data Memory is partitioned into multiple banks,
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>)
and RP0 (STATUS<5>) are the bank select bits:
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
2.2.1
The register file (shown in Figure 2-2 and Figure 2-3)
can be accessed either directly, or indirectly, through
the File Select Register FSR.
On-Chip
Program
Memory
Data Memory Organization
RP1:RP0
GENERAL PURPOSE REGISTER
FILE
CALL, RETURN
RETFIE, RETLW
00
01
10
11
PIC16F73/74
Interrupt Vector
Unimplemented
RESET Vector
Stack Level 8
Stack Level 1
Stack Level 2
Read as ‘0’
PC<12:0>
Page 0
Page 1
PIC16F7X
13
DS30325B-page 13
Bank
0
1
2
3
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
1FFFh