AD9859YSVZ Analog Devices Inc, AD9859YSVZ Datasheet
AD9859YSVZ
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AD9859YSVZ Summary of contents
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FEATURES 400 MSPS internal clock speed Integrated 10-bit DAC 32-bit tuning word Phase noise ≤ –120 dBc/ kHz offset (DAC output) Excellent dynamic performance >75 dB SFDR @ 160 MHz (±100 kHz offset) A Serial I/O control 1.8 ...
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AD9859 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 AD9859—Electrical Specifications ................................................ 3 Absolute Maximum Ratings ............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration ............................................................................. 6 ...
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AD9859—ELECTRICAL SPECIFICATIONS Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5 MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not AGND. Table 1. Parameter REF ...
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AD9859 Parameter TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency Minimum Clock Pulse Width Low Minimum Clock Pulse Width High Maximum Clock Rise/Fall Time Minimum Data Setup Time DVDD_I/O = 3.3 V Minimum Data Setup Time DVDD_I/O = 1.8 V Minimum ...
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ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Maximum Junction Temperature DVDD_I/O (Pin 43) AVDD, DVDD Digital Input Voltage (DVDD_I/O = 3.3 V) Digital Input Voltage (DVDD_I/O = 1.8 V) Digital Output Current Storage Temperature Operating Temperature Lead Temperature (10 sec Soldering) ...
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AD9859 PIN CONFIGURATION I/O UPDATE OSC/REFCLK OSC/REFCLK CRYSTAL OUT CLKMODESELECT LOOP_FILTER Note that the exposed paddle on the bottom of the package forms an electrical connection for the DAC and must be attached to analog ground. Note that Pin 43, ...
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PIN FUNCTION DESCRIPTIONS Table 3. Pin Function Descriptions—48-Lead TQFP/EP Pin No. Mnemonic I/O 1 I/O UPDATE DVDD I 3, 33, 42, 47, DGND 13, 16, 18, AVDD I 19, 25, 27 ...
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AD9859 TYPICAL PERFORMANCE CHARACTERISTICS RBW 10kHz DELTA [T1] REF LVL VBW 10kHz –65.10dB –5dBm SWT 98.19639279MHz 0 1 –10 –20 –30 –40 –50 –60 1 –70 –80 –90 –100 CENTER 100MHz 20MHz/ Figure MHz FCLK = ...
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RBW 1kHz DELTA [T1] VBW REF LVL 1kHz –81.87dB SWT –4dBm 96.19238477kHz –10 –20 –30 –40 –50 –60 –70 –80 1 –90 –100 CENTER 1.16MHz 200kHz/ Figure 10 1.1 MHz, FCLK = 400 MSPS, NBSFDR, ...
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AD9859 Figure 16. Residual Phase Noise with F = 159.5 MHz, F OUT (Green), 4 × 100 MSPS (Red), and 20 × 20 MSPS (Blue) = 400 MSPS Figure 17. Residual Phase Noise with F CLK 4 ×100 MSPS (Red), ...
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THEORY OF OPERATION COMPONENT BLOCKS DDS Core The output frequency ( the DDS is a function of the O frequency of the system clock (SYSCLK), the value of the frequency tuning word (FTW), and the capacity of the ...
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AD9859 DAC Output The AD9859 incorporates an integrated 10-bit current output DAC. Unlike most DACs, this output is referenced to AVDD, not AGND. Two complementary outputs provide a combined full-scale output current (I ). Differential outputs reduce the amount of ...
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Table 5. Register Map Register Name Bit (MSB) (Serial Address) Range Bit 7 Digital <7:0> Power- Down Control Function <15:8> Not Used Register No.1 Automatic (CFR1) <23:16> Sync (0x00) Enable <31:24> <7:0> 0x00 or 0x01, or 0x02 or 0x03: Bypass ...
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AD9859 Control Register Bit Descriptions Control Function Register No. 1 (CFR1) The CFR1 is used to control the various functions, features, and modes of the AD9859. The functionality of each bit is detailed below. CFR1<31:27>: Not Used CFR1<26>: Amplitude Ramp ...
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CFR1<6>: Not Used CFR1<5>: DAC Power-Down Bit CFR1<5> (default). The DAC is enabled for operation. CFR1<5> The DAC is disabled and is in its lowest power dissipation state. CFR1<4>: Clock Input Power-Down Bit CFR1<4> ...
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AD9859 Other Register Descriptions Amplitude Scale Factor (ASF) The ASF register stores the 2-bit auto ramp rate speed value and the 10-bit amplitude scale factor used in the output shaped keying (OSK) operation. In auto OSK operation, ASF <15:14> tells ...
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AUTO Shaped On-Off Keying Mode Operation The auto-shaped on-off keying mode is active when CFR1<25> and CFR1<24> are set. When auto-shaped on-off keying mode is enabled, a single scale factor is internally generated and applied to the multiplier input for ...
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AD9859 External Shaped On-Off Keying Mode Operation The external shaped on-off keying mode is enabled by writing CFR1<25> Logic 1 and writing CFR1<24> Logic 0. When configured for external shaped on-off keying, the content of the ...
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SYSCLK A SYNC_CLK I/O UPDATE DATA IN DATA 1 I/O BUFFERS DATA IN DATA 0 REGISTERS THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE I/O BUFFERS AT POINT B. Synchronizing Multiple AD9859s The ...
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AD9859 There are two phases to a communication cycle with the AD9859. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9859, coincident with the first eight SCLK rising edges. The instruction byte ...
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INSTRUCTION BYTE The instruction byte contains the following information: Table 7. MSB —Bit 7 of the instruction byte determines whether a read or write data transfer occurs after the instruction byte write. ...
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AD9859 When the CFR1<3> bit is 0 and the PWRDWNCTL input pin is high, the AD9859 is put into a fast recovery power-down mode. In this mode, the digital logic and the DAC digital logic are powered down. The DAC ...
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SUGGESTED APPLICATION CIRCUITS RF/IF INPUT AD9859 LPF REFCLK Figure 25. Synchronized LO for Upconversion/Down Conversion PHASE LOOP COMPARATOR FILTER REF SIGNAL AD9859 FILTER TUNING WORLD Figure 26. Digitally Programmable Divide-by-N Function in PLL FREQUENCY MODULATED/ DEMODULATED SIGNAL REFCLK CRYSTAL REFCLK ...
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... Range AD9859YSV −40°C to +105°C AD9859YSV-REEL7 −40°C to +105°C 1 AD9859YSVZ −40°C to +105°C AD9859YSVZ-REEL7 1 −40°C to +105°C 1 AD9859/PCBZ RoHS Compliant Part. ©2004–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...