AD9833BRMZ Analog Devices Inc, AD9833BRMZ Datasheet
AD9833BRMZ
Specifications of AD9833BRMZ
Available stocks
Related parts for AD9833BRMZ
AD9833BRMZ Summary of contents
Page 1
FEATURES Digitally Programmable Frequency and Phase 20 mW Power Consumption MHz to 12.5 MHz Output Frequency Range 28-Bit Resolution (0 MHz Ref Clock) Sinusoidal/Triangular/Square Wave Outputs 2 5.5 V Power ...
Page 2
AD9833–SPECIFICATIONS Parameter SIGNAL DAC SPECIFICATIONS Resolution Update Rate V Max OUT V Min OUT V TC OUT DC Accuracy Integral Nonlinearity Differential Nonlinearity DDS SPECIFICATIONS Dynamic Specifications Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range (SFDR) Wideband (0 to Nyquist) ...
Page 3
TIMING CHARACTERISTICS Parameter Limit MIN min t t – max ...
Page 4
AD9833 ABSOLUTE MAXIMUM RATINGS 25∞C, unless otherwise noted.) A VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V ...
Page 5
Pin Number Mnemonic Power Supply 2 VDD 3 CAP/2 DGND 9 AGND Analog Signal and Reference 1 COMP 10 VOUT Digital Interface and Control 5 MCLK 6 SDATA 7 SCLK 8 FSYNC REV. A PIN CONFIGURATION COMP VOUT ...
Page 6
AD9833–Typical Performance Characteristics 5 5.0 5V 4.5 3V 4.0 3.5 3 MCLK (MHz) TPC 1. Typical Current Consumption vs. MCLK Frequency –40 VDD = ...
Page 7
RWB 100 ST 100 SEC VWB 30 FREQUENCY (Hz) TPC MHz, MCLK f = 2.4 kHz, Frequency OUT Word = 000FBA9 0 –10 ...
Page 8
AD9833 TERMINOLOGY Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The end- points of the transfer function are zero scale, a point 0.5 LSB below the ...
Page 9
Numerically Controlled Oscillator Plus Phase Modulator This consists of two frequency select registers, a phase accumu- lator, two phase offset registers, and a phase offset adder. The main component of the NCO is a 28-bit phase accumulator. Continuous time signals ...
Page 10
AD9833 Control Register The AD9833 contains a 16-bit control register that sets up the AD9833 as the user wants to operate it. All control bits, except MODE, are sampled on the internal negative edge of MCLK. Table II describes the ...
Page 11
Table II. Description of Bits in the Control Register (continued) Bit Name Function D6 SLEEP12 SLEEP12 = 1 powers down the on-chip DAC. This is useful when the AD9833 is used to output the MSB of the DAC data. SLEEP12 ...
Page 12
AD9833 If the user wants to change the entire contents of a frequency regis- ter, two consecutive writes to the same address must be performed since the frequency registers are 28 bits wide. The first write will contain the 14 ...
Page 13
Sinusoidal Output The SIN ROM is used to convert the phase information from the frequency and phase registers into amplitude information that results in a sinusoidal signal at the output. To have a sinusoidal output from the VOUT pin, set ...
Page 14
AD9833 OUT YES CHANGE FSELECT? YES CHANGE FREQUENCY REGISTER? CONTROL REGISTER WRITE (SEE TABLE XI) Figure 7. Flow Chart for AD9833 Initialization and Operation DATA WRITE SEE FIGURE 9 SELECT DATA SOURCES WAIT 8/9 MCLK CYCLES DAC ...
Page 15
DATA WRITE WRITE A FULL 28-BIT WORD TO A FREQUENCY REGISTER? YES (CONTROL REGISTER WRITE) B28 (D13 WRITE TWO CONSECUTIVE 16-BIT WORDS (SEE TABLE V FOR EXAMPLE) WRITE ANOTHER FULL 28-BIT WORD TO A YES FREQUENCY REGISTER? NO ...
Page 16
AD9833 68HC11/68L11* PC7 MOSI SCK *ADDITIONAL PINS OMITTED FOR CLARITY Figure 11. 68HC11/68L11 to AD9833 Interface AD9833 to 80C51/80L51 Interface Figure 12 shows the serial interface between the AD9833 and the 80C51/80L51 microcontroller. The microcontroller is operated in mode 0 ...
Page 17
SCLK 3 SDATA 4 FSYNC 5 DVDD 0 SCLK 13 14 SDATA 15 FSYNC MCLK ...
Page 18
AD9833 OUTLINE DIMENSIONS 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 3.00 BSC 6 10 4.90 BSC 3.00 BSC 1 5 PIN 1 0.50 BSC 0.95 0.85 1.10 MAX 0.23 0.75 0.08 8 0.15 0.27 SEATING 0 ...
Page 19
Revision History Location 6/03—Data Sheet changed from REV REV. A. Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 20
–20– ...