AN82527F8 Intel, AN82527F8 Datasheet - Page 22

• Manufacturer Part Number: AN82527F8
• Description: IC CAN CONTRL 5V AUTOTEMP 44PLCC
• Manufacturer: Intel

Specifications of AN82527F8

• Rohs Status: RoHS non-compliant
• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 50mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 820732

82527
22
14 The timing diagrams for 8-Bit 16-Bit Multiplexed
15 The following A C Characteristics for 8-Bit Mul-
16 The following A C Characteristics for 8-Bit Non-
Intel Modes (Modes 0 1) have been changed to
show ALE rising before CS
tiplexed Non-Intel Modes (Modes 2) have been
changed
Multiplexed Asynchronous Mode (Mode 3) have
been changed
a 1 t
b t
c t
d t
e t
g t
h t
a 1 t
b t
c t
d t
e The note ‘‘E and AS must be tied high in this
k The following definition was added for a
f t
i t
j The following definition was added for a
5 MHz
22 5 ns
100 ns from (2 4) t
t
2 t
has been renamed to t
cation has been decreased to 2 t
145 ns from 4 t
ns
‘‘read cycle without a previous write’’ The
time between the falling edge of E (for the
previous write cycle) and the rising edge of
E (for the current read cycle) is greater than
2 t
‘‘write cycle with a previous write’’ The time
between the falling edge of E (for the previ-
ous write cycle) and the next falling edge of
E (for the current write cycle) is less than
2 t
5 MHz
registers to (2 4) t
(2 4) t
100 pF Load’’ has been removed since
t
Write has been renamed to t
mode’’ has been added
SLAX
EVDV
ELDV
MCLK
ELDV
EHEL
SLEH
CLSL
ELCH
CLDV
CHKH
CHKH
CLKL
MCLK
MCLK
MCLK
MCLK
MCLK
has been added
has been decreased to (2 4) t
has been added
has been increased to 20 ns from 0
has been decreased to 20 ns from
from t
MCLK
for a Write Access with a Previous
for registers except 02H 04H 05H
has been decreased for low speed
is tested with a current source
minimum has been decreased to
maximum has been increased to
comment ‘‘with 3 3 K
a
has been increased to 8 MHz from
has been increased to 8 MHz from
500 ns from 2 t
MCLK
a
MCLK
145 ns
a
MCLK
MCLK
100 ns
a
ELEL
145 ns
a
falls
MCLK
a
and the specifi-
145 ns
CHKL
100 ns from
Pullup and
a
MCLK
MCLK
100 ns
a
a
17 The following A C Characteristics for 8-Bit Non-
18 The following A C Characteristics for Serial In-
19 The note in the A C Testing Input diagram refer-
Multiplexed Synchronous Mode (Mode 3) have
been changed
terface Mode have been changed
enced V
b t
d t
e The following definition was added for a
b t
d t
e t
g The following definition was added for a
a 1 t
c t
a t
c t
f The following definition was added for a
f The following definition was added for a
‘‘read cycle without a previous write’’ The
time between the rising edge of CS
the previous write cycle) and the falling edge
of CS
er than 2 t
‘‘write cycle with a previous write’’ The time
between the rising edge of CS
vious write cycle) and the next rising edge of
CS
2 t
5 MHz
‘‘read cycle without a previous write’’ The
time between the falling edge of E (for the
previous write cycle) and the rising edge of
E (for the current read cycle) is greater than
2 t
‘‘write cycle with a previous write’’ The time
between the falling edge of E (for the previ-
ous write cycle) and the next falling edge of
E (for the current write cycle) is less than
2 t
119 ns
119 ns
84 ns
59 ns
109 ns
ELDZ
AVCL
CHAI
SKHI
SKLO
PDO
SETUP
HOLD
MCLK
MCLK
MCLK
MCLK
OH
(for the current write cycle) is less than
has been added
has been decreased to 59 ns from
minimum has been removed
has been added
has been decreased to 84 ns from
has been decreased to 84 ns from
has been decreased to 84 ns from
has been decreased to 35 ns from
was previously named V
(for the current read cycle) is great-
has been increased to 8 MHz from
MCLK
(for the pre-
IH
(for