DP8419N-70 National Semiconductor, DP8419N-70 Datasheet - Page 15

• Manufacturer Part Number: DP8419N-70
• Description: IC CTRLR 256K DRAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8419N-70

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8419N-70

DP8419 Mode Descriptions
(Refer to Figure 6 ) In mode 5 the selected RAS follows
RASIN immediately as in mode 4 to strobe the row address
into the DRAMs The row address remains valid on the
DP8419 address outputs long enough to meet the t
quirement of the DRAMs (pin 4 RAHS of the DP8419 al-
lows the user two choices of t
dress replaces the row address on the address outputs and
CAS goes low to strobe the columns into the DRAMs WIN
determines whether a read write or read-modify-write is
done
The diagram below illustrates mode 5 automatic control sig-
nal generation
REFRESHING IN CONJUNCTION WITH MODE 5
When using mode 5 to perform memory accesses refresh-
ing may be accomplished
Indicates Dynamic RAM Parameters
(a)
externally (in mode 0 or mode 1)
RAH
) Next the column ad-
(Continued)
TL F 8396 – 16
FIGURE 6 Mode 5 Timing
RAH
re-
15
or
(a) Externally Controlled Refreshing in Mode 0 or Mode 1
All refreshing may be accomplished using external refresh-
es in either mode 0 or mode 1 with R C (RFCK) tied high
(see mode 0 and mode 1 descriptions) If this is desired the
system determines when a refresh will be performed puts
the DP8419 in the appropriate mode and controls the RAS
signals directly with RASIN The on-chip refresh counter is
enabled to the address outputs of the DP8419 when the
refresh mode is entered and increments when RASIN goes
high at the completion of the refresh
(b) Mode 5 Refreshing (hidden) with Mode 1 refreshing
(Refer to Figure 7a ) If RFCK is tied to a clock (see mode 1
description) RFI O becomes a refresh request output and
goes low following RFCK going low if no refresh occurred
while RFCK was high Refreshes may be performed in
mode 5 when the DP8419 is not selected for access (CS is
high) and RFCK is high If these conditions exist the refresh
counter contents appear on the DP8419 address outputs
and all RAS lines follow RASIN so that if RASIN goes low
(an access other than through the DP8419 occurs) all RAS
lines go low to perform the refresh The DP8419 allows only
one refresh of this type for each period of RFCK since
RFCK should be fast enough such that one refresh per peri-
od is sufficient to meet the DRAM refresh requirement
(auto)
(b)
(c)
by a combination of mode 5 (hidden refresh) and
mode 1 (auto-refresh)
by a combination of mode 5 and mode 0
TL F 8396 – 17