DP83902AV/NOPB National Semiconductor, DP83902AV/NOPB Datasheet - Page 47

• Manufacturer Part Number: DP83902AV/NOPB
• Description: IC CTRLR SER NETWORK IN 84PLCC
• Manufacturer: National Semiconductor

Specifications of DP83902AV/NOPB

• Controller Type: Serial Network Interface Controller
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 140mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83902AV; *DP83902AV/NOPB; DP83902AV

13 0 Bus Arbitration and Timing
REMOTE WRITE TIMING
A Remote Write operation transfers data from the I O port
to the local buffer RAM The ST-NIC initiates a transfer by
requesting a byte word via the PRQ The system transfers a
byte-word to the latch via IOW This write strobe is detected
by the ST-NIC and PRQ is removed By removing the PRQ
the Remote DMA holds off further transfers into the latch
until the current byte word has been transferred from the
latch PRQ is reasserted and the next transfer can begin
REMOTE DMA WRITE SPECIAL
CONSIDERATIONS
Setting PRQ Using the Remote Read
Under certain conditions the ST-NIC bus state machine may
issue MWR and PRD before PRQ for the first DMA transfer
of a Remote Write Command If this occurs this could cause
data corruption or cause the remote DMA count to be dif-
ferent from the main CPU count causing the system to ‘‘lock
up’’
To prevent this condition when implementing a Remote
DMA Write the Remote DMA Write command should first
be preceded by a Remote DMA Read command to insure
that the PRQ signal is asserted before the ST-NIC starts its
port read cycle The reason for this is that the state machine
that asserts PRQ runs independently of the state machine
that controls the DMA signals The DMA machine assumes
that PRQ is asserted but actually may not be To remedy
this situation a single Remote Read cycle should be insert-
ed before the actual DMA Write Command is given This will
ensure that PRQ is asserted when the Remote DMA Write is
subsequently executed This single Remote Read cycle is
called a ‘‘dummy Remote Read’’ In order for the dummy
Remote Read cycle to operate correctly the Start Address
should be programmed to a known safe location in the buff-
er memory space and the Remote Byte count should be
programmed to a value greater than 1 This will ensure that
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47
1 ST-NIC asserts PRQ System writes byte word into latch
2 Remote DMA reads contents of port and writes byte
3 Go back to step 1
the master read cycle is performed safely eliminating the
possibility of data corruption
Remote Write with High Speed Buses
When implementing the Remote DMA Write solution with
high speed buses and CPU’s timing may cause the system
to hang Therefore additional considerations are required
A problem occurs when the system can execute the dummy
Remote Read and then start the Remote Write before the
ST-NIC has had a chance to execute the Remote Read If
this happens the PRQ signal will not get set and the Re-
mote Byte Count and Remote Start Address for the Remote
Write operation could be corrupted This is shown by the
hatched waveforms in the following timing diagram The ex-
ecution of the Remote Read can be delayed by the local
DMA operations (particularly during end-of-packet process-
ing)
To ensure the dummy Remote Read does execute a delay
must be inserted between writing the Remote Read Com-
mand and starting to write the Remote Write Start Address
(This time is designated in the next figure by the delay ar-
rows ) The recommended method to avoid this problem is
after the Remote Read command is given to poll both bytes
of the Current Remote DMA Address Registers When the
address has incremented PRQ has been set Software
should recognize this and then start the Remote Write
ST-NIC removes PRQ
word to local buffer memory increments address and
decrements byte count (RBCR0 1)
Steps 1– 3 are repeated until the remote DMA is com-
plete
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