MAX1640EEE Maxim Integrated Products, MAX1640EEE Datasheet - Page 5

• Manufacturer Part Number: MAX1640EEE
• Description: Current Mode PWM Controllers Adj-Out Switch Mode Current Source
• Manufacturer: Maxim Integrated Products

Specifications of MAX1640EEE

• Number Of Outputs: 1
• Duty Cycle (max): 100 %
• Output Voltage: 2 V to 24 V
• Mounting Style: SMD/SMT
• Package / Case: QSOP-16
• Switching Frequency: 500 KHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Synchronous Pin: No
• Topology: Buck
• Case: ssop
• Dc: 99+

______________________________________________________________Pin Description
____________________________Typical Operating Characteristics (continued)
(Circuit of Figure 1, T
PIN
3, 4
10
11
12
13
14
15
16
1
2
5
6
7
8
9
A
B
D1, D0
NAME
PGND
LDOH
TERM
NDRV
PDRV
LDOL
TOFF
GND
CS+
V
A: OUTPUT CURRENT, D0 = D1 = 0 1A/div
B: LOAD VOLTAGE, AC coupled, 500mV/div
REF
SET
CS-
Current Source with Synchronous Rectifier
CC
IN
IN
= 12V, V
CURRENT-MODE CHANGE RESPONSE TIME
_______________________________________________________________________________________
SET
A
Internal, Ground-Referenced Low-Dropout Linear Regulator Output.
Bypass LDOL with a 0.1µF capacitor in parallel with a 4.7µF capacitor to GND.
Off-Time Select Input. A resistor (R
teretic PWM step-down converter. This resistor also sets the period in duty-cycle mode. See Duty-Cycle
Mode and Programming the Off-Time.
Digital Inputs. Select mode of operation (Table 1).
Constant-Current Loop Compensation Input. Bypass CC with a 0.01µF capacitor to GND.
Reference Voltage Output (V
Current Select Input. Program the desired current level by applying a voltage at SET between 0V and V
(I = V
Maximum Output Voltage Termination Input. When V
resets the internal PWM latch, shutting off the external P-channel FET.
Ground
Negative Current-Sense Comparator Input
Positive Current-Sense Comparator Input
High-Current Ground Return for the output drivers
Gate Drive for an optional N-channel FET synchronous rectifier
Gate Drive for the P-channel FET
Internal, Input-Referenced Low-Dropout Linear Regulator Output.
Bypass LDOH with a 0.33µF capacitor to IN.
Power-Supply Input. Input of the internal, low-dropout linear regulators.
= 1V, R
= +25°C, unless otherwise noted.)
LOAD
SET
2ms/div
= 4Ω, NO OUTPUT CAPACITOR
/ 13.3R
SENSE
Adjustable-Output, Switch-Mode
). See Figure 2.
REF
0A
0V
= 2V). Bypass REF with a 0.1µF capacitor to GND.
TOFF
) connected from TOFF to GND programs the off-time for the hys-
FUNCTION
TERM
exceeds the reference voltage, the comparator
A
B
V
A: D0 = D1 = 1 2V/div
B: OUTPUT CURRENT, 0.5A/div
IN
= 12V, R
LOAD
EXITING OFF MODE
= 4Ω
20μs/div
REF
,
5