CY7C68300B-56PVXC Cypress Semiconductor Corp, CY7C68300B-56PVXC Datasheet - Page 20

• Manufacturer Part Number: CY7C68300B-56PVXC
• Description: IC USB 2.0 BRIDGE BULK 56SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C68300B-56PVXC

• Operating Temperature: 0°C ~ 70°C
• Controller Type: USB 2.0 Controller
• Interface: I²C
• Voltage - Supply: 3.15 V ~ 3.45 V
• Current - Supply: 50mA
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Data Rate: 480Mbps
• Supply Voltage Range: 3.15V To 3.45V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: SSOP
• No. Of Pins: 56
• Operating Temperature Max: 85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8-6. EEPROM Organization (continued)
Document 38-08033 Rev. *D
0x06
0x07
0x08
EEPROM
Address
ATA UDMA Enable
ATAPI UDMA Enable
UDMA Modes
Reserved
Multiword DMA mode
PIO Modes
Pin Configurations
BUTTON_MODE
SEARCH_ATA_BUS
BIG_PACKAGE
Field Name
Bit (7)
Enable Ultra DMA data transfer support for ATAPI devices.
If enabled, and if the ATAPI device reports UDMA support
for the indicated modes, the AT2LP will utilize UDMA data
transfers at the highest negotiated rate possible.
0 = Disable ATA device UDMA support.
1 = Enable ATA device UDMA support.
Bit (6)
Enable Ultra DMA data transfer support for ATAPI devices.
If enabled, and if the ATAPI device reports UDMA support
for the indicated modes, the AT2LP will utilize UDMA data
transfers at the highest negotiated rate possible.
0 = Disable ATAPI device UDMA support.
1 = Enable ATAPI device UDMA support.
Bit (5:0)
These bits select which UDMA modes, if supported, are
enabled. Setting to 1 enables. Multiple bits may be set. The
AT2LP will operate in the highest enabled UDMA mode
supported by the device. The AT2LP supports UDMA modes
2, 3, and 4 only.
Bit Descriptions
5
4
3
2
1
0
Bits(7:3)
Must be set to 0.
Bit (2)
This bit selects multi-word DMA. If this bit is set and the drive
supports it, multi-word DMA is used.
Bits(1:0)
These bits select which PIO modes, if supported, are
enabled. Setting to 1 enables. Multiple bits may be set. The
AT2LP will operate in the highest enabled PIO mode
supported by the device. The AT2LP supports PIO modes
0, 3, and 4 only. PIO mode 0 is always enabled by internal
logic.
Bit Descriptions
1
0
Bit (7)
Button mode. Set this bit to 1 to enable ATAPUEN,
PWR500# and DRVPWRVLD to become button inputs
returned on bits 2, 1, and 0 of EP1IN
Bit (6)
Enables a search performed at RESET to detect non-
removable ATA and ATAPI devices. Systems with only a
removable device (like CF readers) will set this bit to 0.
Systems with one removable device and one non-
removable device will set this bit to 1.
Bit (5)
Package Select. Set this bit to 1 when using the 100-pin
device.
Reserved. Must be set to 0.
Enable UDMA mode 4.
Reserved. Must be set to 0.
Enable UDMA mode 2.
Reserved. Must be set to 0.
Reserved. Must be set to 0.
Enable PIO mode 4.
Enable PIO mode 3.
Field Description
CY7C68300B/CY7C68301B
CY7C68320/CY7C68321
Required
Contents
Page 20 of 36
Suggested
Contents
0xD4
0x07
0x78