AAT2552IRN-CAE-T1 Analogic Tech, AAT2552IRN-CAE-T1 Datasheet - Page 23

• Manufacturer Part Number: AAT2552IRN-CAE-T1
• Description: Charge Pumps Total Pwr Solution for Portable App
• Manufacturer: Analogic Tech

Specifications of AAT2552IRN-CAE-T1

• Package / Case: TDFN-16 EP
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Adjustable Output Voltage for the LDO
The output voltage for the LDO can be programmed by
an external resistor divider network.
As shown below, the selection of R4 and R5 is a straight-
forward matter. R5 is chosen by considering the tradeoff
between the feedback network bias current and resistor
value. Higher resistor values allow stray capacitance to
become a larger factor in circuit performance whereas
lower resistor values increase bias current and decrease
efficiency. To select appropriate resistor values, first
choose R5 such that the feedback network bias current
is reasonable. Then, according to the desired V
late R4 according to the equation below. An example
calculation follows.
An R5 value of 59kΩ is chosen, resulting in a small feed-
back network bias current of 1.24V/59kΩ ≈ 21μA. The
desired output voltage is 1.8V. From this information, R4
is calculated from the equation below. The result is R4 =
26.64kΩ. Since 26.64kΩ is not a standard 1%-value,
26.7kΩ is selected. From this example calculation, for
V
output voltages and corresponding resistor values are
provided in Table 4.
SystemPower
2552.2009.01.1.3
OUT
Table 4: Adjustable Resistor Values for the LDO.
R4 Standard 1% Values
= 1.8V, use R5 = 59kΩ and R4 = 26.7kΩ. Example
V
OUT
3.3
2.8
2.5
2.0
1.8
1.5
(V)
TM
R
4
=
⎛
⎝
V
V
OUT
REF
- 1
⎞
⎠
· R
5
(R5 = 59kΩ)
R4 (kΩ)
97.6
75.0
60.4
36.5
26.7
12.4
w w w . a n a l o g i c t e c h . c o m
OUT
, calcu-
Total Power Solution for Portable Applications
Printed Circuit Board
Layout Considerations
For the best results, it is recommended to physically
place the battery pack as close as possible to the
AAT2552 BAT pin. To minimize voltage drops on the PCB,
keep the high current carrying traces adequately wide.
Refer to the AAT2552 evaluation board for a good layout
example (see Figures 6 and 7). The following guidelines
should be used to help ensure a proper layout.
1. The input capacitors (C1, C6) should connect as
2. C4 and L1 should be connected as closely as possi-
3. The feedback pin should be separate from any power
4. The resistance of the trace from PGND should be
5. A high density, small footprint layout can be achieved
closely as possible to ADP, INA, and INB. It is pos-
sible to use two input capacitors for INA and INB.
ble. The connection of L1 to the LX pin should be as
short as possible. Do not make the node small by
using narrow trace. The trace should be kept wide,
direct, and short.
trace and connect as closely as possible to the load
point. Sensing along a high-current load trace will
degrade DC load regulation. Feedback resistors
should be placed as closely as possible to the FBB
pin to minimize the length of the high impedance
feedback trace. If possible, they should also be
placed away from the LX (switching node) and induc-
tor to improve noise immunity.
kept to a minimum. This will help to minimize any
error in DC regulation due to differences in the
potential of the internal signal ground and the power
ground.
using an inexpensive, miniature, non-shielded, high
DCR inductor.
PRODUCT DATASHEET
AAT2552178
23