ISP1761ETGE ST-Ericsson Inc, ISP1761ETGE Datasheet - Page 2

• Manufacturer Part Number: ISP1761ETGE
• Description: IC USB CTRL HI-SPEED 128TFBGA
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1761ETGE

• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1761ET; ISP1761ET

1. General description
2. Features
The ISP1761 is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG)
Controller integrated with advanced NXP slave host controller and the NXP ISP1582
peripheral controller.
The Hi-Speed USB host controller and peripheral controller comply to
Serial Bus Specification Rev. 2.0”
The Enhanced Host Controller Interface (EHCI) core implemented in the host controller is
adapted from
Bus Rev.
Specification Rev.
The ISP1761 has three USB ports. Port 1 can be configured to function as a downstream
port, an upstream port or an OTG port; ports 2 and 3 are always configured as
downstream ports. The OTG port can switch its role from host to peripheral, and
peripheral to host. The OTG port can become a host through the Host Negotiation
Protocol (HNP) as specified in the OTG supplement.
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ISP1761
Hi-Speed Universal Serial Bus On-The-Go controller
Rev. 05 — 13 March 2008
Compliant with
transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
Integrated Transaction Translator (TT) for Original USB (full-speed and low-speed)
peripheral support
Three USB ports that support three operational modes:
Supports OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
Multitasking support with virtual segmentation feature (up to four banks)
High-speed memory controller (variable latency and SRAM external interface)
Directly addressable memory architecture
Generic processor interface to most CPUs, such as Hitachi SH-3 and SH-4, NXP XA,
Intel StrongARM, NEC and Toshiba MIPS, Freescale DragonBall and PowerPC
Reduced Instruction Set Computer (RISC) processors
Configurable 32-bit and 16-bit external memory data bus
Supports Programmed I/O (PIO) and Direct Memory Access (DMA)
Slave DMA implementation on CPU interface to reduce the host system’s CPU load
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Mode 1: Port 1 is an OTG controller port, and ports 2 and 3 are host controller
ports
Mode 2: Ports 1, 2 and 3 are host controller ports
Mode 3: Port 1 is a peripheral controller port, and ports 2 and 3 are host controller
ports
1.0”. The OTG controller adheres to
Ref. 2 “Enhanced Host Controller Interface Specification for Universal Serial
1.3”.
Ref. 1 “Universal Serial Bus Specification Rev.
and support data transfer speeds of up to 480 Mbit/s.
Ref. 3 “On-The-Go Supplement to the USB
2.0”; supporting data
Product data sheet
Ref. 1 “Universal