ISP1161ABM-S ST-Ericsson Inc, ISP1161ABM-S Datasheet - Page 71
ISP1161ABM-S
Manufacturer Part Number
ISP1161ABM-S
Description
IC USB HOST CTRL FULL-SPD 64LQFP
Manufacturer
ST-Ericsson Inc
Datasheet
1.ISP1161ABD.pdf
(135 pages)
Specifications of ISP1161ABM-S
Controller Type
USB 2.0 Controller
Interface
Parallel
Voltage - Supply
3.3V, 5V
Current - Supply
47mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISP1161ABM-S
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
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Philips Semiconductors
Table 46:
9397 750 13962
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcChipID register: bit allocation
15
R
R
0
7
0
10.5.1 HcChipID register (R: 27H)
10.5 HC miscellaneous registers
Table 45:
Read this register to get the ID of the ISP1161A silicon chip. The high byte stands for
the product name (here 61H stands for ISP1161A). The low byte indicates the
revision number of the product including engineering samples.
Code (Hex): 27 — read
Table 47:
Bit
5
4
3
2
1
0
Bit
15 to 0
14
R
R
1
6
0
HcµPInterruptEnable register: bit description
HcChipID register: bit description
Symbol
HC
Suspended
Enable
OPR
Interrupt
Enable
-
EOT
Interrupt
Enable
ATL
Interrupt
Enable
SOF
Interrupt
Enable
Symbol
ChipID[15:0]
13
R
R
1
5
1
Rev. 03 — 23 December 2004
Description
0 — power-up value
1 — enables HC suspended interrupt. When the microprocessor
wants to suspend the HC, the microprocessor must write to the
HcControl register. And when all downstream devices are
suspended, then the HC stops sending SOF; the HC is suspended
by having the HcControl register written into.
0 — power-up value
1 — enables the 32-bit Operational register’s interrupt (if the HC
requires the Operational register to be updated)
reserved
0 — power-up value
1 — enables the EOT interrupt which indicates an end of a
read/write transfer
0 — power-up value
1 — enables ATL interrupt. The time for this interrupt depends on
the number of clock bits set for USB activities in each ms.
0 — power-up value
1 — enables the interrupt bit due to SOF (for the microprocessor
DMA to get ISO data from the HC by first accessing the
HcDMAConfiguration register)
Full-speed USB single-chip host and device controller
Description
ISP1161A’s chip ID
12
R
R
0
4
0
ChipID[15:8]
ChipID[7:0]
11
R
R
0
3
0
10
R
R
0
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
…continued
ISP1161A
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9
0
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R
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