ISP1160BD01TM ST-Ericsson Inc, ISP1160BD01TM Datasheet - Page 25

• Manufacturer Part Number: ISP1160BD01TM
• Description: IC USB HOST CTRL FULL-SPD 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1160BD01TM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1878-2; ISP1160BD/01,118; ISP1160BD01-T

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Product data
9.4.2 Data organization
The data transfer can be done via the PIO mode or the DMA mode. The data transfer
rate can go up to 15 Mbyte/s. In the DMA operation, the single-cycle or multi-cycle
burst modes are supported. Multi-cycle burst modes of 1, 4 or 8 cycles per burst are
supported for the ISP1160.
PTD data is used for every data transfer between a microprocessor and the USB bus,
and the PTD data resides in the buffer RAM. For an OUT or SETUP transfer, the
payload data is placed just after the PTD, after which the next PTD is placed. For an
IN transfer, RAM space is reserved for receiving a number of bytes that is equal to the
total bytes of the transfer. After this, the next PTD and its payload data are placed
(see
Remark: The PTD is defined for both the ATL and ITL type data transfer. For ITL, the
PTD data is put into ITL buffer RAM, and the ISP1160 takes care of the Ping-Pong
action for the ITL buffer RAM access.
The PTD data (PTD header and its payload data) is a structure of DWORD alignment.
This means that the memory address is organized in blocks of 4 bytes. Therefore, the
first byte of every PTD and the first byte of every payload data are located at an
address that is a multiple of 4.
payload data is 14 bytes long, meaning that the last byte of the payload data is at the
location 15H. The next addresses (16H and 17H) are not multiples of 4. Therefore,
the first byte of the next PTD will be located at the next multiple-of-four address (18H).
Fig 18. Buffer RAM data organization.
Figure
18).
Rev. 05 — 24 December 2004
bottom
top
Figure 19
payload data of OUT transfer
payload data of OUT transfer
empty space for IN total data
PTD of OUT transfer
PTD of OUT transfer
PTD of IN transfer
RAM buffer
illustrates an example in which the first
MGT952
Embedded USB Host Controller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
000H
7FFH
ISP1160
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