DS21FT42 Maxim Integrated Products, DS21FT42 Datasheet - Page 56

• Manufacturer Part Number: DS21FT42
• Description: IC FRAMER T1 4X3 12CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FT42

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 225mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS21FT42/DS21FF42
mode, the interrupt will come every 3 ms and the user has a full 3ms to update the TSRs. In the D4
framing mode, there are only two signaling bits per channel (A and B). However in the D4 framing
mode, the framer uses the C and D bit positions as the A and B bit positions for the next multiframe. The
framer will load the values in the TSRs into the outgoing shift register every other D4 multiframe.
14.2 HARDWARE BASED SIGNALING
RECEIVE SIDE
In the receive side of the hardware based signaling, there are two operating modes for the signaling
buffer; signaling extraction and signaling re–insertion.
Signaling extraction involves pulling the
signaling bits from the receive data stream and buffering them over a four multiframe buffer and
outputting them in a serial PCM fashion on a channel–by–channel basis at the RSIG output. This mode
is always enabled. In this mode, the receive elastic store may be enabled or disabled. If the receive
elastic store is enabled, then the backplane clock (RSYSCLK) can be either 1.544 MHz or 2.048 MHz.
In the ESF framing mode, the ABCD signaling bits are output on RSIG in the lower nibble of each
channel. The RSIG data is updated once a multiframe (3 ms) unless a freeze is in effect. In the D4
framing mode, the AB signaling bits are output twice on RSIG in the lower nibble of each channel.
Hence, bits 5 and 6 contain the same data as bits 7 and 8 respectively in each channel. The RSIG data is
updated once a multiframe (1.5 ms) unless a freeze is in effect. See the timing diagrams in Section 24 for
some examples.
The other hardware based signaling operating mode called signaling re–insertion can be invoked by
setting the RSRE control bit high (CCR4.7=1). In this mode, the user will provide a multiframe sync at
the RSYNC pin and the signaling data will be re–aligned at the RSER output according to this applied
multiframe boundary. In this mode, the elastic store must be enabled however the backplane clock can be
either 1.544 MHz or 2.048 MHz.
If the signaling re–insertion mode is enabled, the user can control which channels have signaling re–
insertion performed on a channel–by–channel basis by setting the RPCSI control bit high (CCR4.6) and
then programming the RCHBLK output pin to go high in the channels in which the signaling re–insertion
should not occur. If the RPCSI bit is set low, then signaling re–insertion will occur in all channels when
the signaling re–insertion mode is enabled (RSRE=1). How to control the operation of the RCHBLK
output pin is covered in Section 16.
In both hardware based signaling operating modes, the user has the option to replace all of the extracted
robbed–bit signaling bit positions with ones. This option is enabled via the RFSA1 control bit (CCR4.5)
and it can be invoked on a per–channel basis by setting the RPCSI control bit (CCR4.6) high and then
programming RCHBLK appropriately just like the per–channel signaling re–insertion operates.
The signaling data in the four multiframe buffer will be frozen in a known good state upon either a loss of
synchronization (OOF event), carrier loss, or frame slip. This action meets the requirements of BellCore
TR– TSY–000170 for signaling freezing. To allow this freeze action to occur, the RFE control bit
(CCR4.4) should be set high. The user can force a freeze by setting the RFF control bit (CCR4.3) high.
The four multiframe buffer provides a three multiframe delay in the signaling bits provided at the RSIG
pin (and at the RSER pin if RSRE=1). When freezing is enabled (RFE=1), the signaling data will be held
in the last known good state until the corrupting error condition subsides. When the error condition
subsides, the signaling data will be held in the old state for at least an additional 9 ms (or 4.5 ms in D4
framing mode) before being allowed to be updated with new signaling data.
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