LAN91C96-MU SMSC, LAN91C96-MU Datasheet - Page 31

IC ETHERNET CTLR MAC PHY 100TQFP

LAN91C96-MU

Manufacturer Part Number
LAN91C96-MU
Description
IC ETHERNET CTLR MAC PHY 100TQFP
Manufacturer
SMSC
Datasheet

Specifications of LAN91C96-MU

Controller Type
Ethernet Controller (IEEE 802.3)
Interface
Serial EEPROM
Voltage - Supply
3.3V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
638-1018

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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
5.2
SMSC LAN91C96 5v&3v
8 BIT MODE
((IOis8=1) +
(nEN16=1).
(16BIT=0))
16 BIT MODE
otherwise
16BIT:
IOis8:
nEN16:
8 Bit mode:
Interrupt Structure
The Ethernet interrupt is conceptually equivalent to the LAN91C94 interrupt line, it is the or function of all
enabled interrupts within the Ethernet core. The enabling, reporting, and clearing of these sources is
controlled by the ECOR register. The interrupt structure is similar for LOCAL BUS and PCMCIA modes
with the following exceptions:
PCMCIA uses a single interrupt pin (nIREQ) while LOCAL BUS can use any of four INTR0-3 pins.
8 BIT MODE
16 BIT MODE
(A0=0).(nSBHE=0)
CONFIGURATION REGISTER bit 7
CSR register bit 5
pin nEN16
((IOis8 = 1) + (nMIS16 = 1)
A0
X
X
X
0
1
0
0
1
Table 5.3 - Bus Transactions In PCMCIA Mode
Table 5.4 - Bus Transactions In 68000 Mode
NCE1
0
0
1
0
0
0
1
1
DATASHEET
NCE2
Page 31
Even byte
X
X
X
0
1
1
0
1
D0-7
ILLEGAL ACCESS
Even byte
Even byte
Even byte
Odd byte
Odd byte
D0-7
-
Odd byte
NO CYCLE
NO CYCLE
D8-15
Odd byte
Odd byte
D8-15
-
-
-
Revision 1.0 (10-24-08)

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