LAN9117-MT SMSC, LAN9117-MT Datasheet - Page 123

• Manufacturer Part Number: LAN9117-MT
• Description: IC ETHERNET CTRLR 10/100 100TQFP
• Manufacturer: SMSC

Specifications of LAN9117-MT

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 638-1012

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9117
6.4
SYMBOL
t
t
cycle
t
t
t
t
t
csdv
t
t
asu
don
doff
doh
csh
csl
ah
FIFO_SEL
nCS, nRD
A[2:1]
Data Bus
In this mode the upper address inputs are not decoded, and any read of the LAN9117 will read the
RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is
normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9117. Timing is
identical to a PIO read, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.
Note: The “Data Bus” width is 16 bits
Note: An RX Data FIFO Direct PIO Read cycle begins when both nCS and nRD are asserted. The
RX Data FIFO Direct PIO Reads
DESCRIPTION
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address, FIFO_SEL Setup to nCS, nRD Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and de-
asserted in any order.
Figure 6.3 RX Data FIFO Direct PIO Read Cycle Timing
Table 6.5 RX Data FIFO Direct PIO Read Timing
DATASHEET
123
MIN
45
32
13
0
0
0
0
TYP
Revision 1.5 (07-11-08)
MAX
30
7
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns