UPD720101F1-EA8-A Renesas Electronics America, UPD720101F1-EA8-A Datasheet - Page 5

• Manufacturer Part Number: UPD720101F1-EA8-A
• Description: HOST CTLR USB 2.0 144-FBGA
• Manufacturer: Renesas Electronics America

Specifications of UPD720101F1-EA8-A

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 972-1002

PCI Bus Interface
Arbiter
OHCI Host Controller #1
OHCI Host Controller #2
EHCI Host Controller
Root Hub
PHY
INTA0
INTB0
INTC0
SMI0
PME0
COMPARISON WITH THE
EHCI revision
EHCI
OHCI
Legacy support
Clock
Package
: handles 32-bit 33 MHz PCI bus master and target function which comply with PCI
: is the PCI interrupt signal for OHCI Host Controller #1.
: is the PCI interrupt signal for OHCI Host Controller #2.
: is the interrupt signal which is specified by Open Host Controller Interface Specification
: is the interrupt signal which is specified by PCI-Bus Power Management Interface
: arbitrates among two OHCI host controller cores and one EHCI host controller core.
: handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 1, 3, and 5.
: handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 2 and 4.
: handles high- (480 Mbps) signaling at port 1, 2, 3, 4, and 5.
: handles USB hub function in host controller and controls connection (routing) between
: consists of high-speed transceiver, full-/low-speed transceiver, serializer, deserializer,
: is the PCI interrupt signal for EHCI Host Controller.
specification release 2.2. The number of enabled ports is set by bit in configuration
space.
host controller core and port.
etc.
for USB Rev 1.0a and Enhanced Host Controller Interface Specification Rev 1.0. The
SMI signal of each OHCI Host Controller and EHCI Host Controller appears at this
signal.
Specification release 1.1. Wakeup signal of each host controller core appears at this
signal.
µ
PD720100A
0.95
1
2
Parallel IRQ out support
48 MHz OSC or 30 MHz OSC/X’tal
176-pin BGA (FP) or 160-pin LQFP
Data Sheet S16265EJ5V0DS
µ
PD720100A
1.0
1
2
No parallel IRQ support
48 MHz OSC or 30 MHz X’tal
144-pin BGA (FP) or 144-pin LQFP
µ
PD720101 (2nd generation)
µ
PD720101
3