UPD720102GC-YEB-A Renesas Electronics America, UPD720102GC-YEB-A Datasheet - Page 5
UPD720102GC-YEB-A
Manufacturer Part Number
UPD720102GC-YEB-A
Description
IC HOST CTLR USB2.0 3-PORTS QFP
Manufacturer
Renesas Electronics America
Datasheets
1.UPD720102GC-YEB-A.pdf
(38 pages)
2.UPD720102GC-YEB-A.pdf
(4 pages)
3.UPD720102GC-YEB-A.pdf
(4 pages)
4.UPD720102GC-YEB-A.pdf
(36 pages)
Specifications of UPD720102GC-YEB-A
Controller Type
USB 2.0 Controller
Interface
PCI
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-20°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
120-TQFP
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD720102GC-YEB-A
Manufacturer:
MICREL
Quantity:
11 560
Company:
Part Number:
UPD720102GC-YEB-A
Manufacturer:
RENESAS
Quantity:
664
Company:
Part Number:
UPD720102GC-YEB-A
Manufacturer:
NEC
Quantity:
12
Company:
Part Number:
UPD720102GC-YEB-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD720102GC-YEB-A
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
UPD720102GC-YEB-A/JC
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
PCI Bus Interface
Arbiter
OHCI Host Controller
EHCI Host Controller
Root Hub
PHY
INTA0
SMI0
PME0
: handles 32-bit 33 MHz PCI bus master and target function which comply with PCI
: arbitrates among two OHCI host controller cores and one EHCI host controller core.
: handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling.
: handles high- (480 Mbps) signaling.
: handles USB hub function in host controller and controls connection (routing) between
: consists of high-speed transceiver, full-/low-speed transceiver, serializer, deserializer,
: is the PCI interrupt signal for OHCI Host Controller.
: is the interrupt signal which is specified by open host controller interface specification
: is the interrupt signal which is specified by PCI-bus power management interface
specification revision 2.2. The number of enabled ports is set by bit in configuration
space.
host controller core and port.
etc.
for USB release 1.0a and enhanced host controller interface specification revision 1.0.
The SMI signal of each OHCI host controller and EHCI host controller appears at this
signal.
specification revision 1.1. Wakeup signal of each host controller core appears at this
signal.
Data Sheet S17998EJ4V0DS
μ
PD720102
3