MAX5940BESA+T Maxim Integrated Products, MAX5940BESA+T Datasheet - Page 6

• Manufacturer Part Number: MAX5940BESA+T
• Description: IC IEEE 802.3AF PD INTFC 8-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX5940BESA+T

• Controller Type: Powered Device Interface Controller (PD)
• Interface: IEEE 802.3af
• Voltage - Supply: 48V
• Current - Supply: 1mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The PD front-end section of the MAX5940_ operates in 3
different modes, PD detection signature, PD classifica-
tion, and PD power, depending on its input voltage (V
GND - V
ate with or without the optional diode bridge while still
complying with the IEEE 802.3af standard (see Figure 4).
In detection mode, the power source equipment (PSE)
applies two voltages on V
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
6
MAX5940A/
MAX5940C
_______________________________________________________________________________________
1, 7
—
—
2
3
4
5
6
8
EE
PIN
). All voltage thresholds are designed to oper-
MAX5940B/
MAX5940D
—
1
2
3
4
5
6
7
8
Detection Mode (1.4V ≤ V
Detailed Description
RCLASS
PGOOD
PGOOD
IN
NAME
UVLO
GATE
GND
N.C.
OUT
V
in the range of 1.4V to 10.1V
EE
Operating Modes
No Connection. Not internally connected.
Undervoltage Lockout Programming Input for Power Mode. When UVLO is above its
threshold, the device enters power mode. Connect UVLO to V
undervoltage lockout threshold. Connect UVLO to an external resistor-divider to define a
threshold externally. The series resistance value of the external resistors must add to 25.5kΩ
(±1%) and replaces the detection resistor. To keep the device in undervoltage lockout, pull
UVLO to between V
Classification Setting. Add a resistor from RCLASS to V
and 2).
Gate of Internal N-Channel Power MOSFET. GATE sources 10µA when the device enters
power mode. Connect an external 100V ceramic capacitor (C
program the inrush current. Pull GATE to V
and classification functions operate normally when GATE is pulled to V
Negative Input Power. Source of the integrated isolation N-channel power MOSFET. Connect
V
Output Voltage. Drain of the integrated isolation N-channel power MOSFET.
Power-Good Indicator Output, Active-High, Open-Drain. PGOOD is referenced to OUT.
PGOOD goes high impedance when V
V
Connect PGOOD to the ON pin of a downstream DC-DC converter.
Power-Good Indicator Output, Active-Low, Open-Drain. PGOOD is referenced to V
PGOOD is pulled to V
Otherwise, PGOOD goes high impedance. Connect PGOOD to the ON pin of a downstream
DC-DC converter.
Ground. GND is the positive input terminal.
EE
EE
. Otherwise, PGOOD is pulled to OUT (given that V
to -48V.
IN
≤ 10.1V)
TH,G,UVLO
IN
EE
=
when V
and V
(1V step minimum), and then records the current mea-
surements at the two points. The PSE then computes
ΔV/ΔI to ensure the presence of the 25.5kΩ signature
resistor. In this mode, most of the MAX5940_ internal cir-
cuitry is off and the offset current is less than 10µA.
If the voltage applied to the PD is reversed, install pro-
tection diodes on the input terminal to prevent internal
damage to the MAX5940_ (see the Typical Application
Circuits). Since the PSE uses a slope technique (ΔV/ΔI)
to calculate the signature resistance, the DC offset due
to the protection diodes is subtracted and does not
affect the detection process.
OUT
REF,UVLO
is within 1.2V of V
OUT
FUNCTION
EE
is within 1.2V of V
to turn off the internal MOSFET. The detection
.
EE
OUT
EE
and when GATE is 5V above V
to set a PD class (see Tables 1
is at least 5V below GND).
EE
GATE
EE
and when GATE is 5V above
to use the default
) from GATE to OUT to
Pin Description
EE
.
EE
.
EE
.