MAX5940DESA+T Maxim Integrated Products, MAX5940DESA+T Datasheet - Page 3

• Manufacturer Part Number: MAX5940DESA+T
• Description: IC IEEE 802.3AF PD INTFC 8-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX5940DESA+T

• Controller Type: Powered Device Interface Controller (PD)
• Interface: IEEE 802.3af
• Voltage - Supply: 48V
• Current - Supply: 1mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS (continued)
(V
Typical values are at T
Note 1: All min/max limits are production tested at +85°C. Limits at +25°C and -40°C are guaranteed by design.
Note 2: The input offset current is illustrated in Figure 1.
Note 3: Effective differential input resistance is defined as the differential resistance between GND and V
Note 4: Classification current is turned off whenever the IC is in power mode.
Note 5: See Table 2 in the PD Classification Mode section. R
Note 6: See the Thermal Dissipation section for details.
Note 7: When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5kΩ (±1%), the turn-
Note 8: When the UVLO input voltage is below V
Note 9: An input voltage or V
Note 10: Guaranteed by design.
Note 11: PGOOD references to OUT while PGOOD references to V
UVLO Input Ground Sense
Threshold (Note 8)
UVLO Input Ground Sense Glitch
Rejection
Power Turn-Off Voltage,
Undervoltage Lockout Deglitch
Time (Note 9)
Isolation Switch N-Channel
MOSFET On-Resistance
Isolation Switch N-Channel
MOSFET Off-Threshold Voltage
GATE Pulldown Switch Resistance
GATE Charging Current
GATE High Voltage
PGOOD, PGOOD Assertion V
Threshold
PGOOD, PGOOD Assertion V
Threshold
PGOOD, PGOOD Output Low
Voltage (Note 11)
PGOOD Leakage Current (Note 11)
PGOOD Leakage Current (Note 11)
IN
= (GND - V
resistance. See Figure 1.
bias current and the current drawn by R
on threshold set-point for the power mode is defined by the external resistor-divider. Make sure the voltage on the UVLO
pin does not exceed its maximum rating of 8V when V
MAX5940A/MAX5940B/MAX5940C/MAX5940D to exit power-on mode (as long as the input voltage remains above an opera-
ble voltage level of 12V).
PARAMETER
EE
) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = V
_______________________________________________________________________________________
A
= +25°C. All voltages are referenced to V
OUT
GATE
IEEE 802.3af PD Interface Controller
UVLO
glitch below their respective thresholds shorter than or equal to t
V
SYMBOL
V
TH,G,UVLO
t
V
OFF_DLY
OLDCDC
V
V
V
OUTEN
R
GSTH
GSEN
GATE
R
I
ON
G
G
DISC
TH,G,UVLO,
UVLO = V
V
Output current =
300mA, V
measured between
OUT and V
OUT = GND, V
< 1µA
Power-off mode, V
UVLO = V
V
I
V
V
Hysteresis
(GATE - V
Hysteresis
I
(GND - 5V)
GATE = high, GND - V
GATE = V
GATE
SINK
IN
GATE
OUT
GATE
.
, V
= 2mA; for PGOOD, OUT ≤
UVLO
- V
= 1µA
= 2V
= 5.75V
EE
GATE
EE
EE
EE
EE
the MAX5940B sets the UVLO threshold internally.
EE
, |V
DISC
falling
) increasing, OUT = V
, PGOOD - V
IN
For Power-Over-Ethernet
for MAX5940B
EE
OUT
CONDITIONS
GATE
is at the maximum voltage (MAX5940B only).
= 6V,
EE
and R
, unless otherwise noted.) (Note 1)
IN
.
- V
- V
= 12V,
EE
OUT
CL
EE,
| decreasing,
T
(Note 10)
T
EE
A
A
must be ±1%, 100ppm or better. I
output current
= +25°C
= +85°C
= 67V
= 67V
EE
EE
, T
A
= -40°C to +85°C, unless otherwise noted.
MIN
0.32
5.59
1.16
4.62
0.5
50
5
OFF_DLY
TYP
5.76
1.23
4.76
0.6
0.8
38
10
70
80
EE
7
CLASS
without any external
does not cause the
MAX
includes the IC
5.93
1.31
4.91
440
1.1
1.5
0.4
80
15
1
1
UNITS
mV
mV
mV
ms
µA
µA
µA
µs
Ω
Ω
V
V
V
V
V
3