DP83815DUJB/NOPB National Semiconductor, DP83815DUJB/NOPB Datasheet - Page 14
DP83815DUJB/NOPB
Manufacturer Part Number
DP83815DUJB/NOPB
Description
IC MEDIA ACCESS CONTROL 160-LBGA
Manufacturer
National Semiconductor
Datasheet
1.DP83815DVNGNOPB.pdf
(108 pages)
Specifications of DP83815DUJB/NOPB
Controller Type
Ethernet Controller, MAC/BIU
Interface
PCI
Voltage - Supply
3.3V
Current - Supply
170mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
160-LBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
*DP83815DUJB
*DP83815DUJB/NOPB
DP83815DUJB
*DP83815DUJB/NOPB
DP83815DUJB
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DP83815DUJB/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
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3.0 Functional Description
3.1 MAC/BIU
The MAC/BIU is a derivative design from the DP83810
(Euphrates). The original MAC/BIU design has been
optimized to improve logic efficiency and enhanced to add
features consistent with current market needs and
specification compliance. The MAC/BIU design blocks are
discussed in this section.
3.1.1 PCI Bus Interface
This block implements PCI v2.2 bus protocols, and
configuration space. Supports bus master reads and writes
to CPU memory, and CPU access to on-chip register
space. Additional functions provided include: configuration
32
PCI Bus
Interface
EEPROM
93C46
Serial
32
32
32
32
32
Figure 3-2
32
15
(Continued)
Boot ROM/
MAC/BIU
Flash
Pkt Recog
Rx Filter
Rx Buffer Manager
Tx Buffer Manager
SRAM
MIB
Logic
Data FIFO
Data FIFO
Functional Block Diagram
14
control, serial EEPROM access with auto configuration
load, interrupt control, power management control with
support for PME or CLKRUN function.
3.1.1.1 Byte Ordering
The DP83815 can be configured to order the bytes of data
on the AD[31:0] bus to conform to little endian or big
endian ordering through the use of the Configuration
Register, bit 0 (CFG:BEM). By default, the device is in little
endian ordering. Byte ordering only affects data FIFOs.
Register information remains bit aligned (i.e. AD[31] maps
to bit 31 in any register space, AD[0] maps to bit 0, etc.).
16
32
32
MAC/BIU
Rx MAC
Tx MAC
Rev O
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