Z8523L10VSG Zilog, Z8523L10VSG Datasheet - Page 58

• Manufacturer Part Number: Z8523L10VSG
• Description: IC CTRL SCC 10MHZ 3.3V 44-PLCC
• Manufacturer: Zilog

Specifications of Z8523L10VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: Bus
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 2.5mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Product: I/O Controller
• Operating Supply Voltage: - 0.3 V to 7 V
• Supply Current (max): 9 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4731

Table 24. Write Register 15
PS005308-0609
Bit
R/W
Reset
R = Read W = Write X = Indeterminate
Bit
Position
7
6
5
4
3
2
1
0
Read Registers
The ESCC contains ten read registers (eleven, counting the receive buffer RR8) in each
channel. Four of these may be read to obtain status information (RR0, RR1, RR10, and
RR15).
Two registers, RR12 and RR13, are read to learn the BRG time constant. RR2 contains
either the unmodified interrupt vector, Channel A, or the vector modified by status infor-
mation, Channel B.
RR3 contains the Interrupt Pending (IP) bits for Channel A.
RR6 and RR7 contain the information in the SDLC Frame Status FIFO, but is only read
when WR15 bit 2 is 1. If WR7’ bit 6 is 1, Write Registers WR3, WR4, WR5, and WR10
can be read as RR9, RR4, RR5, and RR14, respectively.
Table 40
R/W
7
1
on page 69 list the format of the read registers.
Value
6
1
Description
Break/Abort Interrupt Enable
Tx Underrun/EOM Interrupt Enable
CTS Interrupt Enable
Sync/Hunt
DCD Interrupt Enable
SDLC FIFO Enable
Zero Count Interrupt Enable
WR7’ SDLC Feature Enable
5
1
4
1
W
3
0
Table 25
2
0
Product Specification
on page 54 through
Z80230/Z85230/L
1
0
Programming
0
0
53