CY7C68033-56LTXC Cypress Semiconductor Corp, CY7C68033-56LTXC Datasheet - Page 27

• Manufacturer Part Number: CY7C68033-56LTXC
• Description: IC USB CTLR NAND NX2LP 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C68033-56LTXC

• Controller Type: USB 2.0 NAND Flash Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 43mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Data Bus Width: 8 bit
• Interface Type: NAND Flash, USB
• Maximum Operating Temperature: + 70 C
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3686 - DEV KIT USB 2.0 PER OLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Document #: 001-04247 Rev. *D
Slave FIFO Asynchronous Packet End Strobe
Table 13.Slave FIFO Asynchronous Packet End Strobe Parameters
Slave FIFO Output Enable
Table 14.Slave FIFO Output Enable Parameters
Slave FIFO Address to Flags/Data
Table 15.Slave FIFO Address to Flags/Data Parameters
t
t
t
t
t
t
t
PEpwl
PWpwh
XFLG
OEon
OEoff
XFLG
XFD
Parameter
Parameter
Parameter
PKTEND Pulse Width LOW
PKTEND Pulse Width HIGH
PKTEND to FLAGS Output Propagation Delay
SLOE Assert to FIFO DATA Output
SLOE Deassert to FIFO DATA Hold
FIFOADR[1:0] to FLAGS Output Propagation Delay
FIFOADR[1:0] to FIFODATA Output Propagation Delay
Figure 13. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
FIFOADR [1.0]
Figure 15. Slave FIFO Address to Flags/Data Timing Diagram
DATA
SLOE
FLAGS
Figure 14. Slave FIFO Output Enable Timing Diagram
PKTEND
DATA
FLAGS
Description
Description
Description
t
t
PEpwl
t
OEon
XFLG
t
XFLG
t
XFD
N
[15]
N+1
t
PEpwh
t
OEoff
Min.
Min.
Min.
50
50
CY7C68033/CY7C68034
[13]
[13]
Max.
Max.
Max.
10.5
10.5
10.7
14.3
115
[9]
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Unit
Unit
Unit
ns
ns
ns
ns
ns
ns
ns