VNC2-48Q1B-REEL FTDI, Future Technology Devices International Ltd, VNC2-48Q1B-REEL Datasheet - Page 51

• Manufacturer Part Number: VNC2-48Q1B-REEL
• Description: IC USB HOST VINCULUM-II 48QFN
• Manufacturer: FTDI, Future Technology Devices International Ltd
• Series: Vinculum-IIr

Specifications of VNC2-48Q1B-REEL

• Mfg Application Notes: Vinculum-II IO Cell Description AppNote Vinculum-II Debug Interface Description AppNote Vinculum-II IO Mux Explained AppNote Vinculum-II PWM Example AppNote Migrating Vinculum Designs AppNote
• Controller Type: USB 2.0 Controller
• Interface: SPI Serial, USB, UART
• Voltage - Supply: 1.62 V ~ 1.98 V
• Current - Supply: 25mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 768-1048-2; VNC2-48Q1A-REEL

6.3.6.1 SPI Setup Bit Encoding
The VNC1L compatible SPI interface differs from most other implementations in that it uses a 12 clock
sequence to transfer a single byte of data. In addition to a „Start‟ state, the SPI master must send two
setup bits which indicate data direction and target address. The encoding of the setup bits is shown in
Table 20. A single data byte is transmitted in each SPI transaction, with the most significant bit
transmitted first.
After each transaction VNC2 returns a single status bit. This indicates if a Data Write was successful or a
Data Read was valid.
Table 20 SPI Setup Bit Encoding
The VNC2 SPI interface uses 4 signal lines: SCLK, SS, MOSI and MISO. The signals MOSI, MISO and SS
are always clocked on the rising edge of the SCLK signal.
SS signal must be raised high for the duration of the entire transaction. For data transactions, the SS
must be released for at least one clock cycle after a transaction has completed. It is not necessary to
release SS between Status Read operations.
The „Start‟ state of MOSI and SS high on the rising edge of SCLK initiates the transfer. The transfer
finishes after 13 clock cycles, and the next transfer starts when MOSI is high during the rising edge of
CLK.
The following Figure 6-16 and
Table
Direction
(R/W)
1
1
0
0
21
give details of the bus timing requirements.
Address
Target
Copyright © 2010 Future Technology Devices International Limited
0
1
0
1
VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet
Status Read
Data Write
Data Read
Operation
N/A
Retrieve byte from Transmit Buffer
Add byte to Receive Buffer
Read SPI Interface Status
Document No.: FT_000138
Clearance No.: FTDI#
Meaning
N/A
Version -
143
1.2
51