VNC2-32Q1B-REEL FTDI, Future Technology Devices International Ltd, VNC2-32Q1B-REEL Datasheet - Page 43

• Manufacturer Part Number: VNC2-32Q1B-REEL
• Description: IC USB HOST VINCULUM-II 32QFN
• Manufacturer: FTDI, Future Technology Devices International Ltd
• Series: Vinculum-IIr

Specifications of VNC2-32Q1B-REEL

• Mfg Application Notes: Vinculum-II IO Cell Description AppNote Vinculum-II Debug Interface Description AppNote Vinculum-II IO Mux Explained AppNote Vinculum-II PWM Example AppNote Migrating Vinculum Designs AppNote
• Controller Type: USB 2.0 Controller
• Interface: SPI Serial, USB, UART
• Voltage - Supply: 1.62 V ~ 1.98 V
• Current - Supply: 25mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 768-1050-2; VNC2-32Q1A-REEL

6.3 Serial Peripheral Interface – Slave
Figure 6-4 SPI Slave block diagram
VNC2 has two SPI Slave modules both of which use four wire interfaces: MOSI, MISO, CLK and SS#.
Their main purpose is to send data from main memory to the attached SPI master, and / or receive data
and send it to main memory. The SPI Slave is controlled by the internal CPU using internal memory
mapped I/O registers. It operates from the main system clock, although sampling of input data and
transmission of output data is controlled by the SPI clock (CLK). An SPI transfer can only be initiated by
the SPI Master and begins with the slave select signal being asserted. This is followed by a data byte
being clocked out with the master supplying CLK. The master always supplies the first byte, which is
called a command byte. After this the desired number of data bytes are transferred before the
transaction is terminated by the master de-asserting slave select. An SPI Master is able to abort a
transfer at any time by de-asserting its SS# output. This will cause the Slave to end its current transfer
and return to idle state.
6.3.1 SPI Slave Signal Descriptions
Available
Package
11, 15,
19, 24,
28, 39,
43, 47,
51, 57,
12, 16,
20, 25,
29, 40,
44, 48,
52, 58,
13, 17,
22, 26,
31, 41,
45, 49,
55, 59,
64 Pin
pins
61
62
63
Available
Package
11, 15,
20, 31,
35, 41,
21, 32,
36, 42,
13, 18,
22, 33,
37, 43,
48 Pin
12,16,
pins
45
46
47
Copyright © 2010 Future Technology Devices International Limited
External - SPI Master
Available
Package
12, 24,
14, 25,
32 Pin
11, 23
pins
VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet
29
30
31
spi_s0_mosi
spi_s1_mosi
spi_s0_miso
spi_s1_miso
spi_s0_clk
spi_s1_clk
Name
MOSI
MISO
CLK
SS#
Output
Input
Input
Type
Synchronous data from master to slave
Synchronous data from slave to master
VNC2 - SPI Slave
Master In Slave Out
Mater Out Slave In
Slave clock input
Document No.: FT_000138
Clearance No.: FTDI#
Description
Version -
143
1.2
43