LTC4267IGN-1#TRPBF Linear Technology, LTC4267IGN-1#TRPBF Datasheet - Page 28

• Manufacturer Part Number: LTC4267IGN-1#TRPBF
• Description: IC POE 802.3AF INTERFACE 16SSOP
• Manufacturer: Linear Technology

Specifications of LTC4267IGN-1#TRPBF

• Controller Type: Power over Ethernet Controller (POE)
• Interface: IEEE 802.3af
• Current - Supply: 3mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP
• Linear Misc Type: Negative Voltage
• Package Type: SSOP N
• Operating Supply Voltage (max): -57V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Lead Free Status / Rohs Status: Compliant

LTC4267-1
APPLICATIO S I FOR ATIO
28
For the LTC4267-1 switching regulator, the current loop
through C1, T1 primary, Q1, and R
careful layout attention. (Refer to Figure 11.) Because of
the high switching current circulating in this loop, these
components should be placed in close proximity to each
other. In addition, wide copper traces or copper planes
should be used between these components. If vias are
necessary to complete the connectivity of this loop,
placing multiple vias lined perpendicular to the fl ow of
current is essential for minimizing parasitic resistance and
reducing current density. Since the switching frequency
and the power levels are substantial, shielding and high
frequency layout techniques should be employed. A low
current, low impedance alternate connection should be
employed between the PGND pins of the LTC4267-1 and
the PGND side of R
This Kelvin sensing will ensure an accurate representation
of the sense voltage is measured by the LTC4267-1.
The placement of the feedback resistors R1 and R2 as
well as the compensation capacitor C
in the accuracy of the output voltage, the stability of the
main control loop, and the load transient response. In
an isolated design application, R1, R2, and C
placed as close as possible to the error amplifi er’s input
with minimum trace lengths and minimum capacitance.
In a nonisolated application, R1, and R2 should be placed
SENSE
U
, away from the high current loop.
U
W
SENSE
C
is very important
must be given
C
U
should be
as close as possible to the V
and C
LTC4267-1.
In essence, a tight overall layout of the high current loop
and careful attention to current density will ensure suc-
cessful operation of the LTC4267-1 in a PD.
The PD interface section of the LTC4267-1 is relatively im-
mune to layout problems. Excessive parasitic capacitance
on the R
adjacent to the V
tive or capacitive may inadvertently disable the signature
resistance. To ensure consistent behavior, the SIGDISA
pin should be electrically connected and not left fl oating.
Voltages in a PD can be as large as –57V, so high voltage
layout techniques should be employed.
Electro Static Discharge and Surge Protection
The LTC4267-1 is specifi ed to operate with an absolute
maximum voltage of –100V and is designed to tolerate
brief overvoltage events. However, the pins that interface
to the outside world (primarily V
routinely see peak voltages in excess of 10kV. To protect
the LTC4267-1, it is highly recommended that a transient
voltage suppressor be installed between the diode bridge
and the LTC4267-1 (D3 in Figure 2).
C
should be placed close to the I
CLASS
pin should be avoided. The SIGDISA pin is
PORTP
pin and any coupling, whether resis-
FB
PORTN
pin of the LTC4267-1
TH
and V
/RUN pin of the
PORTP
) can
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