TMC2074-NU SMSC, TMC2074-NU Datasheet - Page 86

• Manufacturer Part Number: TMC2074-NU
• Description: IC CTRL CIRC 128VTQFP PERIPH MOD
• Manufacturer: SMSC
• Series: CircLink™r

Specifications of TMC2074-NU

• Controller Type: I/O Controller
• Interface: Transceiver
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1024

Dual Mode CircLink™ Controller
Datasheet
TKNRETF (bit 7)
This bit indicates that a token retry is performed. Refer to section 2.4.1 - Reducing Token Loss for details.
This bit is cleared by writing a 1or by a software reset.
ACKNAKF (bit 6)
This bit indicates that counter measures to handle corrupted ACK/NAK data have been implemented.
Refer to section 2.4.1 for details. This bit is cleared by writing a 1 or by a software reset.
HUBWDTO (bit 5)
This bit indicates that the HUB unit has been reset which was caused by timeout of watchdog timer. This is
done to prevent the direction control circuit of the HUB unit from hanging-up. A timeout occurs if the
transmit signal from HUB is continuously active for 3.27 ms or more. (when using 2.5 Mbps. At 5 Mbps, the
value is half -> 1.64 ms)
This timeout causes the HUB unit and two CMI units to be automatically reset. (If the HUB unit is OFF, the
CMI units are not reset.) This bit is cleared by writing a 1or by a software reset.
CPERR (bit 4)
This bit is set if the CP field of the preceding packet is of a value that exceeded the page boundary, or is
between 00h and 02h, both of which are invalid CP settings.
Refer to section 2.5.3, Packet Data Structure for details. This bit is cleared by writing a 1 or by a software
reset.
1: Packet including invalid CP field is sent, 0: Normal packet is sent
COM (bit 3)
This bit is set to 1 if there is an interrupt from the ARCNET core. Be sure to set the COMR0 mask register
bits when required.
This bit is set to 1 when the interrupt is generated by EXCNAK, RECON, NXTIDERR and TA bit in the
mask register of COMR0.
FBENR (bit 2)
Both FBENR and TXERR bits are set if there is no response to FBE . If FBENR is set, it is possible to
determine that data is transmitted to a node that is not receiving properly, thus identifying failures based on
deformed packet data. This bit is cleared by writing a 1, issuing a send command, or by a software reset.
TXERR (bit 1)
This bit is set if sending fails. Be aware that this function is the opposite of that of the ARCNET-original
TMA bit. This bit is cleared by writing a 1 , issuing the send command, or by a software reset.
TA (bit 0)
This bit is the same as the TA bit of the COMR0: ARCNET status register. (Refer to that register for
details.) This bit becomes 0 only while the send command is being issued.
Combination and meaning of transmission status
TA
TXERR
FBENR
Meaning
Revision 0.2 (10-23-08)
Page 86
SMSC TMC2074
DATASHEET