ISP1761BEUM ST-Ericsson Inc, ISP1761BEUM Datasheet - Page 107
![IC USB OTG CONTROLLER HS 128LQFP](/photos/6/81/68198/isp1761beum_sml.jpg)
ISP1761BEUM
Manufacturer Part Number
ISP1761BEUM
Description
IC USB OTG CONTROLLER HS 128LQFP
Manufacturer
ST-Ericsson Inc
Datasheet
1.ISP1761BEUM.pdf
(164 pages)
Specifications of ISP1761BEUM
Controller Type
USB Peripheral Controller
Interface
Serial
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
568-1888-2
ISP1761BE,518
ISP1761BE-T
ISP1761BE,518
ISP1761BE-T
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NXP Semiconductors
Table 102. Interrupt Configuration register (address 0210h) bit allocation
ISP1761_5
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
10.5.3 Interrupt Configuration register
R/W
CDBGMOD[1:0]
7
1
1
Table 101. Mode register (address 020Ch) bit description
This 1 byte register determines the behavior and polarity of the INT output. The bit
allocation is shown in
or NYET, it will generate interrupts depending on three Debug mode fields.
CDBGMOD[1:0] — Interrupts for the control endpoint 0
DDBGMODIN[1:0] — Interrupts for the DATA IN endpoints 1 to 7
DDBGMODOUT[1:0] — Interrupts for the DATA OUT endpoints 1 to 7
The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow you
to individually configure when the ISP1761 sends an interrupt to the external
microprocessor.
Bit INTPOL controls the signal polarity of the INT output: active HIGH or LOW, rising or
falling edge. For level-triggering, bit INTLVL must be made logic 0. By setting INTLVL to
logic 1, an interrupt will generate a pulse of 60 ns (edge-triggering).
Bit
6
5
4
3
2
1 to 0
R/W
6
1
1
Symbol
SNDRSU
GOSUSP
SFRESET
GLINTENA
WKUPCS
-
Table 104
DDBGMODIN[1:0]
R/W
5
1
1
Table
Rev. 05 — 13 March 2008
Description
Send Resume: Writing logic 1, followed by logic 0 will generate an
upstream resume signal of 10 ms duration, after a 5 ms delay.
Go Suspend: Writing logic 1, followed by logic 0 will activate suspend
mode.
Soft Reset: Writing logic 1, followed by logic 0 will enable a
software-initiated reset to the ISP1761. A soft reset is similar to a
hardware-initiated reset using the RESET_N pin.
Global Interrupt Enable: Logic 1 enables all interrupts. Individual
interrupts can be masked by clearing the corresponding bits in the
DcInterruptEnable register.
When this bit is not set, an unmasked interrupt will not generate an
interrupt trigger on the interrupt pin. If the global interrupt, however, is
enabled while there is any pending unmasked interrupt, an interrupt
signal will immediately be generated on the interrupt pin. If the interrupt
is set to pulse mode, the interrupt events that were generated before the
global interrupt is enabled may be dropped.
Wake up on Chip Select: Logic 1 enables wake-up through a valid
register read on the ISP1761. A read will invoke the chip clock to restart.
A write to the register before the clock is stable may cause
malfunctioning.
reserved
lists the available combinations.
102. When the USB SIE receives or generates an ACK, NAK
R/W
4
1
1
DDBGMODOUT[1:0]
R/W
3
1
1
…continued
R/W
2
1
1
Hi-Speed USB OTG controller
unchanged
INTLVL
R/W
1
0
© NXP B.V. 2008. All rights reserved.
ISP1761
unchanged
INTPOL
106 of 163
R/W
0
0
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