USB3300-EZK SMSC, USB3300-EZK Datasheet - Page 27

• Manufacturer Part Number: USB3300-EZK
• Description: IC USB HOST/OTG PHY ULPI 32-QFN
• Manufacturer: SMSC
• Type: Hi Speed USB Host Devicer

Specifications of USB3300-EZK

• Controller Type: USB 2.0 Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1034

Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface
Datasheet
SMSC USB3300
6.1.4.10
6.1.4.11
SessEnd Fall
IdGnd Fall
Reserved
HostDisconnect
VbusValid
SessValid
SessEnd
IdGnd
Reserved
HostDisconnect Latch
VbusValid Latch
SessValid Latch
SessEnd Latch
IdGnd Latch
Reserved
FIELD NAME
FIELD NAME
FIELD NAME
USB Interrupt Status Register: Address = 13h (read only with auto clear)
USB Interrupt Status: Address = 14h (read only with auto clear)
BIT
BIT
BIT
7:5
7:5
7:5
3
4
0
1
2
3
4
0
1
2
3
4
DEFAULT
DEFAULT
DEFAULT
1b
1b
0h
0b
0b
0b
0b
0b
0h
0b
0b
0b
0b
0b
0h
DATASHEET
Generate an interrupt event notification when SessEnd changes
from high to low.
Generate an interrupt event notification when IdGnd changes
from high to low.
Driven low.
Current value of the UTMI+ Hostdisconnect output. Applicable
only in host mode.
Current value of the UTMI+ Vbusvalid output.
Current value of the UTMI+ SessValid output.
Current value of the UTMI+ SessEnd output.
Current value of the UTMI+ IdGnd output.
Driven low.
Set to 1b by the PHY when an unmasked event occurs on
Hostdisconnect. Cleared when this register is read. Applicable
only in host mode.
Set to 1b by the PHY when an unmasked event occurs on
VbusValid. Cleared when this register is read.
Set to 1b by the PHY when an unmasked event occurs on
SessValid. Cleared when this register is read.
Set to 1b by the PHY when an unmasked event occurs on
SessEnd. Cleared when this register is read.
Set to 1b by the PHY when an unmasked event occurs on
IdGnd. Cleared when this register is read.
Driven low.
27
DESCRIPTION
DESCRIPTION
DESCRIPTION
Revision 1.08 (11-07-07)