Z8523010PSG Zilog, Z8523010PSG Datasheet - Page 10

• Manufacturer Part Number: Z8523010PSG
• Description: IC 10MHZ ESCC 40-DIP
• Manufacturer: Zilog

Specifications of Z8523010PSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: Bus
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 5mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Operating Supply Voltage: 5 V
• Supply Current (max): 9 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3921; Z8523010PSG

PS005303-0907
When used as DMA Request line (WR14 bit 2 is 1), the timing for the deactivation request
can be programmed in Write Register 7
deactivated with the same timing as the W/REQ pin. If 0, the deactivation timing of DTR/
REQ pin is four clock cycles, the same as in the Z80C30/Z85C30.
W/REQA, W/REQB (Wait/request (Output, Open-drain When Programmed For WAIT
Function, Driven High And Low When Programmed For Request Function)).
dual-purpose outputs may be programmed as REQUEST lines for a DMA controller or as
WAIT lines to synchronize the CPU to the ESCC data rate. The reset state is WAIT.
RxDA, RxDB (Receive Data (inputs, active High)).
standard Transistor-Transistor Logic (TTL) levels.
RTxCA, RTxCB (Receive/Transmit Clocks (Input, Active Low)).
programmed to several modes of operation. In each channel, RTxC may supply the fol-
lowing:
•
•
•
These pins can also be programmed for use with the respective SYNC pins as a crystal
oscillator. The receive clock may be 1, 16, 32, or 64 times the data rate in ASYNCHRO-
NOUS modes.
TxDA, TxDB (Transmit Data (Output, Active High)).
standard TTL levels.
TRxCA, TRxCB (Transmit/Receive Clocks (Input or Output, Active Low)).
These pins can be programmed in several different modes. When configured as an input,
the TRxC may supply the receive clock and/or the transmit clock. When configured as an
output, TRxC can echo the clock output of the Digital Phase-Locked Loop, the crystal
oscillator, the BRG or the transmit clock.
PCLK (Clock (Input)).
signals. PCLK is a TTL level signal. PCLK is not required to have any phase relationship
with the master system clock.
IEI (Interrupt Enable In (Input, Active High)).
daisy chain when there is more than one interrupt-driven device. A High IEI indicates that
no higher priority device has an Interrupt Under Service (IUS) or is requesting an
interrupt.
IEO (Interrupt Enable Out (Output, Active High)).
the CPU is not servicing an ESCC interrupt. During an Interrupt Acknowledge Cycle, IEO
is also driven Low if the ESCC is requesting an interrupt. IEO can be connected to the
next lower priority device’s IEI input, and in this case inhibits interrupts from lower prior-
ity devices.
Receive clock and/or the transmit clock
Clock for the baud rate generator (BRG)
Clock for the Digital Phase-Locked Loop
This clock is the master ESCC clock used to synchronize internal
’
(WR7’) bit 4. If this bit is 1, the DTR/REQ pin is
IEI is used with IEO to form an interrupt
IEO is High only if IEI is High and
These inputs receive serial data at
These output transmit serial data at
Product Specification
These pins can be
Z85230/Z80230
Pin Descriptions
These
5