ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 3

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Silicon Errata Issues
1. Module: PHY (Receive)
FIGURE 1:
© 2009 Microchip Technology Inc.
Note:
On rare occasions, in 10Base-T Half-Duplex
mode, a collision will cause the immediately follow-
ing packet to be received incorrectly. This causes
the packet to be dropped. This condition may
occur on an average of one to four times per
10,000 collisions.
Full-Duplex mode and 100Base-TX modes are
unaffected by this issue. Typical modern networks
are deployed using Ethernet switching technology
and will not experience any collisions or packet
loss due to this issue. In the uncommon case that
an affected network infrastructure is used, upper
layer communications protocols, such as TCP, will
normally perform automatic retransmission to
ensure that no application data is lost.
Work around
None.
Affected Silicon Revisions
A2
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A2).
10Base-T MAU EYE DIAGRAM
ENC424J600/624J600
2. Module: PHY (Transmit)
When transmitting random data in 10Base-T
mode, the PHY transmit waveform slightly violates
the MAU eye diagram keep-out zones specified in
the IEEE 802.3™ Std. 2005, Section 14.3.1.2.1.
Specifically, the waveform amplitude is slightly too
high for ‘0’ to ‘1’ and ‘1’ to ‘0’ bit transitions when
tested against the twisted-pair model, as shown in
Figure 1.
This issue applies only to 10 Mbps speed and is
unlikely to cause compatibility problems in real
networks. When terminated with a 100Ω resistor
without the twisted-pair model, the transmit wave-
form stays within the amplitude limits of +2.2V to
+2.8V and -2.2V to -2.8V required by the standard.
Work around
None.
Affected Silicon Revisions
A2
X
DS80477A-page 3