ENC28J60-I/ML Microchip Technology, ENC28J60-I/ML Datasheet - Page 14

• Manufacturer Part Number: ENC28J60-I/ML
• Description: IC ETHERNET CTRLR W/SPI 28QFN
• Manufacturer: Microchip Technology

Specifications of ENC28J60-I/ML

• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.1 V to 3.6 V
• Supply Current (max): 180 mA
• Package: 28QFN EP
• Standard Supported: IEEE 802.3
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII|MIIM
• Data Rate: 10 Mbps
• Host Interface: SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC28J60
3.1
The Control registers provide the main interface
between the host controller and the on-chip Ethernet
controller logic. Writing to these registers controls the
operation of the interface, while reading the registers
allows the host controller to monitor operations.
The Control register memory is partitioned into four
banks,
BSEL1:BSEL0, in the ECON1 register. Each bank is
32 bytes long and addressed by a 5-bit address value.
The last five locations (1Bh to 1Fh) of all banks point to a
common set of registers: EIE, EIR, ESTAT, ECON2 and
ECON1. These are key registers used in controlling and
monitoring the operation of the device. Their common
mapping allows easy access without switching the bank.
The ECON1 and ECON2 registers are discussed later in
this section.
TABLE 3-1:
DS39662C-page 12
Address
Bank 0
0Ch
0Dh
1Ch
1Dh
0Ah
0Bh
0Eh
1Ah
1Bh
1Eh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Fh
10h
12h
13h
14h
15h
16h
17h
18h
19h
1Fh
11h
Control Registers
selectable
ERXWRPTH
EDMADSTH
ERXRDPTH
ERXWRPTL
EDMADSTL
ERXRDPTL
EDMANDH
EDMACSH
EDMASTH
EDMANDL
EDMACSL
EDMASTL
EWRPTH
ERXNDH
Reserved
ERDPTH
EWRPTL
ETXNDH
ERXSTH
ERXNDL
ERDPTL
ETXSTH
ETXNDL
ETXSTL
ERXSTL
ECON2
ECON1
ESTAT
Name
ENC28J60 CONTROL REGISTER MAP
EIR
EIE
—
—
by
the
Address
Bank 1
bank
0Ch
0Dh
1Ch
1Dh
0Ah
0Bh
0Eh
1Ah
1Bh
1Eh
0Fh
1Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
10h
12h
13h
14h
15h
16h
17h
18h
19h
11h
select
ERXFCON
EPKTCNT
EPMCSH
Reserved
Reserved
Reserved
EPMCSL
EPMOH
EPMM0
EPMM1
EPMM2
EPMM3
EPMM4
EPMM5
EPMM6
EPMM7
EPMOL
ECON2
ECON1
ESTAT
Name
EHT0
EHT1
EHT2
EHT3
EHT4
EHT5
EHT6
EHT7
EIR
EIE
—
—
bits,
Preliminary
Address
Bank 2
Some of the available addresses are unimplemented.
Any attempts to write to these locations are ignored
while reads return ‘0’s. The register at address 1Ah in
each bank is reserved; read and write operations
should not be performed on this register. All other
reserved registers may be read, but their contents must
not be changed. When reading and writing to registers
which contain reserved bits, any rules stated in the
register definition should be observed.
Control registers for the ENC28J60 are generically
grouped as ETH, MAC and MII registers. Register
names starting with “E” belong to the ETH group.
Similarly, registers names starting with “MA” belong to
the MAC group and registers prefixed with “MI” belong
to the MII group.
0Ah
0Bh
0Ch
0Dh
0Eh
1Ah
1Bh
1Ch
1Dh
1Eh
0Fh
1Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
10h
12h
13h
14h
15h
16h
17h
18h
19h
11h
MACLCON1
MACLCON2
MIREGADR
MAMXFLH
MAMXFLL
MABBIPG
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MACON1
MACON3
MACON4
MAIPGH
MAIPGL
MICMD
MIWRH
ECON2
ECON1
MIWRL
MIRDH
MIRDL
ESTAT
Name
EIE
EIR
—
—
—
© 2008 Microchip Technology Inc.
Address
Bank 3
0Ch
0Dh
1Ch
1Dh
1Eh
0Ah
0Bh
0Eh
0Fh
1Ah
1Bh
1Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
10h
12h
13h
14h
15h
16h
17h
18h
19h
11h
EBSTCON
EFLOCON
EBSTCSH
EBSTCSL
ECOCON
Reserved
Reserved
MAADR5
MAADR6
MAADR3
MAADR4
MAADR1
MAADR2
EBSTSD
EPAUSH
EPAUSL
EREVID
MISTAT
ECON2
ECON1
ESTAT
Name
EIE
EIR
—
—
—
—
—
—
—
—
—